multiplexer and demultiplexer experiment

Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates.

Introduction.

The function of a multiplexer is to select the input of any ‘n’ input lines and feed that to one output line. The function of a de-multiplexer is to inverse the function of the multiplexer and the shortcut forms of the multiplexer. The de-multiplexers are mux and demux. Some multiplexers perform both multiplexing and de-multiplexing operations.

1) Multiplexer

Multiplexer is a device that has multiple inputs and a single line output. The select lines determine which input is connected to the output, and also to increase the amount of data that can be sent over a network within certain time. It is also called a data selector.

Multiplexers are classified into four types:

a) 2-1 multiplexer (1 select line) b) 4-1 multiplexer (2 select lines) c) 8-1 multiplexer(3 select lines) d) 16-1 multiplexer (4 select lines)

1.1) 4x1 Multiplexer

4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1 and one output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.One of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

2) De-multiplexer

De-multiplexer is also a device with one input and multiple output lines. It is used to send a signal to one of the many devices. The main difference between a multiplexer and a de-multiplexer is that a multiplexer takes two or more signals and encodes them on a wire, whereas a de-multiplexer does reverse to what the multiplexer does.

De-multiplexer are classified into four types:

a)1-2 demultiplexer (1 select line) b)1-4 demultiplexer (2 select lines) c)1-8 demultiplexer (3 select lines) d)1-16 demultiplexer (4 select lines)

2.2) 1x4 De-multiplexer

1x4 De-Multiplexer has one input Data(D), two selection lines, S0 & S1 and four outputs Y0, Y1, Y2 & Y3. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

Multiplexer and Demultiplexer – The ultimate guide

When we transfer data, there are a few things that we need to consider to ensure that our transfers are quick, lossless, and efficient. However, transmitting data requires bandwidth.

Or let us put it in even simpler terms. From a layman perspective, if we have a high number of connections or wires between two points, you can transfer a more massive amount of data. However, transmission lines, connections, even the traces on a circuit board are an expensive commodity — both cost and real estate wise.

You ideally need a system where you can transfer the most data using the least connections and cost. That is one of the core aspects of communication system design.

In this post, we will look at the multiplexer and demultiplexer circuits.  We will also tabulate the multiplexer and demultiplexer truth tables.

What is a multiplexer?

Basically, it switches between one of the many input lines and connects them one by one to the output. It decides which input line to switch to using a control signal.

How does a multiplexer work?

To understand the design and working of a multiplexer, we will dive right in. We will start by designing the simplest of digital multiplexers: the 2:1 mux.

2:1 multiplexer truth table

In this way, the multiplexer acts as a switching circuit. Now, as we increase the number of inputs, the number of select lines will increase too.

Can you calculate how many select lines would be present in this mux?

If you are unable to answer these questions, you still have the formula we saw above to count on. For n inputs, m select lines, where n=2^m. 4 = 2^m, therefore, m =2. We need two select lines for a 4:1 mux.

4:1 multiplexer truth table

S0S1 = 00 (0 – decimal value), I0 is connected to the output.

S0S1 = 10 (2), I2 is the output

Solving for output using the method we saw in the post for comparators . Output is 1 when I0 = 1 and S0 = 0 and S1 = 0 OR when I1 = 1 and S0 = 0 and S1 = 1 and so on we get

Plotting the circuit for the above equation we get the following logic circuit for a 4:1 multiplexer.

What are the uses of a multiplexer?

The applications of a multiplexer include

How to join multiplexers?

Let’s make a 4:1 mux using 2:1 multiplexers. We know that a 2:1 mux has two inputs and one select line. So joining two 2:1 multiplexers will give us four inputs, two outputs (we need only 1), and two select lines. So how do we proceed?

How do you reduce three select lines to two select lines?

How to design 8:1 multiplexer, 16:1 multiplexer, and so on?

You can also go the opposite way and use a multiplexer with more inputs than required as a smaller mux. Here’s an 8:1 multiplexer being used as a 2:1 multiplexer.

How to make logic gates using multiplexers?

As with a lot of logical circuits, making gates using mux also does not have a method written in stone. You can try alternative designs and arrive at the same logical conclusions.

Let’s start with the NOT gate. We know that it just inverts the input and has one input. If we consider the select line to be the input, apply a HIGH logic at Io, and LOW logic at I1, we get a NOT gate.

Similarly, by applying some logic, you can derive all other gates using just 2:1 Mux. Try it! It’s a good exercise for increasing logical ability.

What is a demultiplexer?

In a demux, we have n output lines, one input line, and m select lines. The relation between the number of output lines and the number of select lines is the same as we saw in a multiplexer. That is, 2^m = n. Depending on the value of the binary number formed by the select lines, any one of the output lines connects to the input line.

The general symbol of a demultiplexer is shown below.

How does a demultiplexer work?

To understand the working of a demultiplexer, we will straight away design one. The 1:2 demux is the simplest of all demultiplexers. We have one input, two outputs, and one select line (2^m = 2, therefore m=1). Let’s write the truth table for this demux.

1:2 demultiplexer t ruth table

In this way, a demultiplexer distributes data from one data line to multiple data lines.

Truth table for a 1:4 demultiplexer

As you can see, this truth table is shorter than the one for the 4:1 mux. This is because instead of taking both the possible values of the input, we just took it as I. The resulting equations will be the same. When you have large truth tables, tricks like this are handy and will make it easier for you to get to the equations you need.

Y0 = S0’S1′

What are the applications of a demultiplexer?

Umair has a Bachelor’s Degree in Electronics and Telecommunication Engineering. He also holds a Post-Graduate Diploma in Embedded System Design from the Centre of Development of Advanced Computing (Pune, India). Currently, Umair is pursuing his MS in Electronics Engineering from the University of Hertfordshire (Hatfield, UK).

Related courses to Multiplexer and Demultiplexer – The ultimate guide

8085 Microprocessors Course

Vhdl course, cmos - ic design course.

A free course as part of our VLSI track that teaches everything CMOS. Right from the physics of CMOS to designing of logic circuits using the CMOS inverter.

Leave a Reply Cancel reply

Multiplexer and Demultiplexer

Multiplexer and demultiplexer are two devices very important in data communications. As the name implies, their functions are opposite to each other (similar to encoder and decoder ). These devices are used for sharing a device between two or more applications.

Consider, for instance, a decoder for seven-segment display. If we have a four-digit decimal number to display then we need four seven-segment displays and each one requires a decoder. However, by using a multiplexer and a demultiplexer, one unit of a decoder can be shared between the four displays.

Multiplexer

The role of a multiplexer is to receive the information from different senders and deliver it to its output. By receiving a select data, a multiplexer is instructed from which sender to receive data.

We may say, a single multiplexer (we may have multiple units of multiplexer) at a time selects information from one of many input lines and directs it to a single output. The select data then can successively address other inputs. N select lines can address 2 N data input lines as senders of information.

Demultiplexer

The role of the demultiplexer is to receive information from one line input and deliver it to one of many output lines or devices as specified by the select data, which is also received by the demultiplexer. By receiving a select signal demultiplexer channels the main data to a particular address.

In other words, a simple demultiplexer receives one channel of input data and directs it to one of the many output channels, as selected by the select data. Depending on the select data bit size a maximum of 2, 4, 8, 16, 32, and so forth can share the main data.

Figure 1 shows the schematic of a pair of multiplexer/demultiplexer for transferring data over a single line.

Figure 1 Schematic of a multiplexer and a demultiplexer.

In the arrangement in Figure 1 , if the select data in the multiplexer have a pattern based on which the data lines are continuously selected in an orderly manner, the same pattern can be given to the demultiplexer, and consequently, after synchronization, all data are sent and received over the line between the two. This is what happens in communication devices.

Figure 2 illustrates a very simplified circuit for the example of the driver for a seven-segment display.

• The multiplexer in this example directs a set of four incoming data to its output, which goes to the decoder (driver).
• After decoding is done, the information for a to g segments are put on a data bus (a bus is the main line in an electric or electronic device that provides voltage or data to all components) that is shared between the four display units. Only one of the units will light up at a time because the select data are also sent to the demultiplexer, based on which only one of the display units is connected to the positive voltage.
• In here it is assumed that the display segments have a common anode that needs to be connected to the positive terminal. In general, the LED’s in a seven-segment display can be connected in two ways. They have either a common anode or a common cathode. Their other sides are then connected to the driver data bus.

Figure 2 Simplified circuit showing multiplexer and demultiplexer for seven-segment display units sharing a driver.

Multiplexer and De-multiplexer

• First Online: 31 August 2023

Cite this chapter

• Farzin Asadi 2  

Part of the book series: Synthesis Lectures on Electrical Engineering ((SLEE))

147 Accesses

Multiplexer (or Mux) is a device that selects between several digital (or analog) input signals and forwards the selected input to a single output line. The selection is directed by a separate set of digital inputs known as select lines. A multiplexer makes it possible for several input signals to share one device or resource, for example, one analog-to-digital converter or one communications transmission medium, instead of having one device per input signal. Multiplexers can also be used to implement Boolean functions of multiple variables. Conversely, a de-multiplexer (or Demux) is a device taking a single input and selecting signals of the output of the compatible mux, which is connected to the single input, and a shared selection line. A multiplexer is often used with a complementary demultiplexer on the receiving end. This chapter studies the multiplexer and demultiplexers.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save.

• Get 10 units per month
• Download Article/Chapter or eBook
• 1 Unit = 1 Article or 1 Chapter
• Cancel anytime
• Available as PDF
• Read on any device
• Instant download
• Own it forever
• Available as EPUB and PDF
• Durable hardcover edition
• Dispatched in 3 to 5 business days
• Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References for Further Study

Asadi F (2022) Essential circuit analysis using proteus®. Springer. https://doi.org/10.1007/978-981-19-4353-9

Article   Google Scholar  

Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://doi.org/10.1007/978-3-030-89850-2

Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-3-031-09853-6

Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/978-3-031-25122-1

Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-02021-6

https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits

https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits

Download references

Author information

Authors and affiliations.

Department of Electrical and Electronics Engineering, Maltepe University, Istanbul, Türkiye

Farzin Asadi

You can also search for this author in PubMed   Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2024 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Asadi, F. (2024). Multiplexer and De-multiplexer. In: Digital Circuits Laboratory Manual. Synthesis Lectures on Electrical Engineering. Springer, Cham. https://doi.org/10.1007/978-3-031-41516-6_4

Download citation

DOI : https://doi.org/10.1007/978-3-031-41516-6_4

Published : 31 August 2023

Publisher Name : Springer, Cham

Print ISBN : 978-3-031-41515-9

Online ISBN : 978-3-031-41516-6

eBook Packages : Synthesis Collection of Technology (R0)

Share this chapter

Anyone you share the following link with will be able to read this content:

Sorry, a shareable link is not currently available for this article.

Provided by the Springer Nature SharedIt content-sharing initiative

• Publish with us

Policies and ethics

• Find a journal
• Track your research

• Skip to main content
• Skip to primary sidebar

Electronics Coach

All About Electronics

Difference Between Multiplexer (MUX) and Demultiplexer (DEMUX)

The major factor that differentiates multiplexer and demultiplexer is their ability to accept multiple input and single input respectively. The multiplexer also known as a MUX operates on several inputs but provide a single output. As against demultiplexer also known as DEMUX simply reverses the operation of MUX and operates on single input but transmits the data to multiple outputs.

It is noteworthy here that multiplexer acts as data selector thus provide a single output from several inputs. However, demultiplexer acts as a data distributor and generates several outputs with a single input.

We will discuss some other major differences between MUX and DEMUX but before that have a look towards the contents to be discussed under this article.

Content: Multiplexer vs Demultiplexer

• Comparison Chart
• Key Differences

Comparison chart

Definition of  Multiplexer

It is a logic circuit that allows a single output to get generated by accepting multiple data input. Multiplexer consists of the control signal or data select input that concludes the output from several inputs. Thus, also known as the data selector.

It is referred to as many to one circuit due to its ability to select the single output from multiple inputs.

The figure below shows the circuit of a MUX including input, output and control signals.

It works as a multi-position switch which is digitally controlled by the control signals. Here, the select lines determine which input will get switched to output among several inputs. As we can see in the figure shown above that n input signal is fed to a MUX, containing m control signals. However, only 1 data source is transmitted to output.

A relation exists between the input and select lines which is noteworthy and is given by:

: m is the select lines and n is the input lines

One can have several configurations of multiplexer depending on input lines and the control signal applied to it.

Let us have a look at 4 to 1 multiplexer that consists of 4 input signal along with 2 control signals, in order to provide a single output.

Here, 4 input bits applied to the MUX are D 0 , D 1 , D 2 , D 3 and the control signals are a and b. So, any data input can be transmitted to output on changing the level of the control signal.

The truth table for the multiplexer is shown below. Let us consider 4 separate cases in order to understand the variation in output by controlling the level of control signals.

Case 1 : Consider that both the applied control signals a and b are low i.e., 0. In such a condition due to the presence of NOT gate inputs I 1 and I 2 of only AND gate 1 is high. So, if the input bit of D 0 is high then the output is high and if the input of D 0 is low then AND gate generates its output as 0.

Thus, with control signal level 00 only A 1 is enabled and all others get disable hence output achieved is the reflection of data bit associated with A 1 .

Case 2 : When control signal a is low and b is high then it causes AND gate 2 to be enabled as I 1 and I 2 of A 2 will be high. So, input bit D 1 decides the output of A 2 . If D1 is high, the output will be 1 otherwise 0.

Case 3 : Now consider that level of control signal a is high and that of b is low. This enables only AND gate 3 as inputs I 1 and I 2 of A 3 is high in this condition. So, applied input bit D 2 will provide the desired bit at the output.

Case 4 : Let us now consider the case when the level of both the applied control signals is high or 1. Then due to this only gate, A 4 gets enabled while all others get disabled. Due to this, the output will be the result of applied input D 3 .

Definition of  Demultiplexer

Demultiplexer basically reverses the operation of a multiplexer. It switches a single input to several outputs.

Here also control signal plays a major role by deciding the output to which the input is to be passed. It is also known as data distributor as it allows a single input to be distributed among multiple outputs.

Let’s have a look at the DEMUX configuration shown below that have only one input but m control and n output lines.

Moving further have a look at 1:4 demultiplexer consisting of data bit D, with 2 control signals a and b. Here, Z 0 , Z 1 , Z 2 , Z 3 are the 4 output provided by the demultiplexer.

As we have already explained that for a particular value of control signal only a single AND gate is enabled while all others get disabled.

The truth table for a 1:4 DEMUX is shown below

Demultiplexer circuit also plays a major role in the communication system as sometimes parallel data reception is required. Thus, for such applications, these circuits are used.

Key Differences Multiplexer and Demultiplexer

• Both Multiplexers and Demultiplexers are combinational logic circuits used in communication system but their operation is exactly reverse of each other as one operates on multiple inputs and other on a single input.
• When we talk about data conversion technique then it is not difficult to understand that MUX performs parallel to serial conversion as it requires several inputs. However, DEMUX on a reverse note performs serial to parallel conversion as multiple outputs are achieved in its case.
• Multiplexer with the help of control signals selects the particular input that has to be transmitted at the output. On the contrary, Demultiplexer utilizes the control signal and allows us to have multiple outputs.
• Another key difference exists for MUX and DEMUX is that multiplexer is N to 1 device but demultiplexer is 1 to N device.

A communication system requires both multiplexer and demultiplexer due to its bidirectional nature but the operation of the two are exactly opposite to each other. The presence of control signals plays a crucial role in the working of MUX and DEMUX.

Related Terms:

• Difference between Demultiplexer and Decoder
• Demultiplexer
• Digital Multiplexer
• Difference Between Encoder and Decoder
• Difference between Combinational and Sequential Logic Circuit

Reader Interactions

Leave a reply cancel reply.

Your email address will not be published. Required fields are marked *

Save my name, email, and website in this browser for the next time I comment.

• Methodology
• Laboratory Techniques and Procedures

Lab Report on Implementations of 2 to 1 MUX, 4 to 1 MUX, and 1 to 4 Demultiplexer

• October 2023

• Bangladesh University of Business and Technology

Discover the world's research

• 25+ million members
• 160+ million publication pages
• 2.3+ billion citations
• Recruit researchers
• Join for free
• Login Email Tip: Most researchers use their institutional email address as their ResearchGate login Password Forgot password? Keep me logged in Log in or Continue with Google Welcome back! Please log in. Email · Hint Tip: Most researchers use their institutional email address as their ResearchGate login Password Forgot password? Keep me logged in Log in or Continue with Google No account? Sign up

Take Online Course

This is an online, interactive course that contains instructions, multimedia, and assessments where you can learn at your own pace.

Learn more about NI’s platform for online, interactive courses

Take online lab.

This is an online, interactive lab that contains instructions, multimedia, and assessments where you can learn at your own pace.

Teach Online Lab

This is an online, interactive lab that contains instructions, multimedia, and assessments where students can learn at their own pace. As an instructor, you can create and edit instances of this lab, assign them to students, and view student progress.

Teach Online Course

This is an online, interactive course that contains instructions, multimedia, and assessments where students can learn at their own pace. As an instructor, you can create and edit instances of this course, assign them to students, and view student progress.

About Thinkscape

• Innovations
• Academic & Research
• Teaching Resources

Multiplexers and Demultiplexers

• Educator Community |
• Access My Courses |
• Bookmarks |

by Enable Education

Student materials, instructor resources, skills required.

• Introductory physics and circuits 

Requirements

Multisim is a circuit simulation tool built for educators to teach analog, digital, and power electronics by connecting simulation to experimentation.  Learn more

NI ELVIS II/II+

The NI Educational Laboratory Virtual Instrumentation Suite (NI ELVIS) is a versatile laboratory platform that enables educators to teach over 20 different courses across science and engineering departments. The NI ELVIS integrates 12 common lab instruments including an oscilloscope, function... Learn more

Digital System Development Board

The Digital System Development Board (DSDB) is a digital electronics and FPGA trainer board with a Zync 7020 FPGA and 19 different periphrials to program and experiment to get a hands-on understanding of digital electronics. Programmable with Multisim, HDL, or LabVIEW, the DSDB takes students from... Learn more

DETAILED REQUIREMENTS

Required software.

• NI ELVISmx Software Suite 14.0 or later (Includes Multsim 14.0 or later and required driver) -  Download
• Vivado Webpack HL - Download  

Required Hardware

• NI ELVIS II or II+ platform
• Oscilloscope

Related Resources

These labs have related concepts that can expand student experience.

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

• View all journals
• Explore content
• About the journal
• Publish with us
• Sign up for alerts
• Open access
• Published: 28 September 2017

Frequency-division multiplexer and demultiplexer for terahertz wireless links

• Jianjun Ma 1 ,
• Nicholas J. Karl 1 ,
• Sara Bretin 2 ,
• Guillaume Ducournau 2 &
• Daniel M. Mittleman 1  

Nature Communications volume  8 , Article number:  729 ( 2017 ) Cite this article

11k Accesses

102 Citations

89 Altmetric

Metrics details

• Electrical and electronic engineering
• Photonic devices
• Terahertz optics

The development of components for terahertz wireless communications networks has become an active and growing research field. However, in most cases these components have been studied using a continuous or broadband-pulsed terahertz source, not using a modulated data stream. This limitation may mask important aspects of the performance of the device in a realistic system configuration. We report the characterization of one such device, a frequency multiplexer, using modulated data at rates up to 10 gigabits per second. We also demonstrate simultaneous error-free transmission of two signals at different carrier frequencies, with an aggregate data rate of 50 gigabits per second. We observe that the far-field spatial variation of the bit error rate is different from that of the emitted power, due to a small nonuniformity in the angular detection sensitivity. This is likely to be a common feature of any terahertz communication system in which signals propagate as diffracting beams not omnidirectional broadcasts.

Similar content being viewed by others

Generalized Kramers–Kronig receiver for coherent terahertz communications

Multi-kilometre and multi-gigabit-per-second sub-terahertz communications for wireless backhaul applications

Formation of gigahertz pulse train by chirped terahertz pulses interference

Introduction.

The volume of wireless data traffic is increasing exponentially and will surpass 24 exabytes per month by 1 2019. To accommodate this trend, future generations of wireless networks will require much higher capacity for data throughput. One favored solution is to operate at higher carrier frequencies, beyond 100 GHz 2 , 3 , 4 , 5 . Recent years have witnessed rapidly growing interest in the development of components to enable wireless communications in the terahertz (THz) range. One of the earliest examples is modulators, first discussed almost 20 years ago 6 , with rapid improvements continuing to be reported 7 , 8 , 9 , 10 . Other examples include power splitters 11 , 12 , filters 13 , 14 , phase shifters 15 , beam-steering devices 16 , 17 , 18 , passive reflectors for engineered multipath environments 19 , 20 , and multiplexers and demultiplexers (mux/demux) 21 , 22 . Despite these efforts, many important components of such networks remain at a very immature stage of development, including components for mux and demux. Mux and demux of non-interfering data streams is universally employed in existing communication systems and, in combination with advanced modulation schemes 23 , can be an efficient method to achieve the eventual data rate target of Tb/s. In the THz range, where frequency bands may not be continuous over a broad spectral range due to atmospheric attenuation 24 or regulatory restrictions 25 , frequency-division multiplexing is even more of a compelling need.

We have recently proposed an architecture for waveguide-to-free space mux/demux based on a leaky waveguide 21 . This concept exploits the highly directional nature of THz signals, which are much more like beams than omnidirectional broadcasts. A particular client in a network would be assigned a spectral band based on its location, such that only signals within that spectral band are sent to the location of the particular client. The device can accommodate mobility by tuning the carrier frequency to account for changes in the client location; this process would likely rely on beam-sounding techniques using legacy bands at lower frequencies 26 . Alternatively, multiple clients can be served simultaneously by mux/demux of multiple signals lying in distinct frequency bands.

The operating principle of the leaky-wave device is straightforward. It is based on a metal parallel-plate waveguide (PPWG), which has proven to be a versatile platform for manipulation of THz signals 27 , 28 . The waveguide has a narrow slot opened in one of the metal plates, which (in the demux configuration) allows some of the guided wave to leak out into free space. Similar leaky-wave designs have been used in the RF community for many years 29 , but their use in the THz range has so far been limited 21 , 30 , 31 . The frequency of the emitted radiation at a given angle is determined by a phase-matching constraint:

where k 0 =  2π v / c 0 is the wave vector for free space with v as the frequency of the signal and c 0 as the speed of light in vacuum. ϕ is the propagation angle of the free-space mode relative to the waveguide propagation axis. The frequency-dependent propagation constant for the lowest-order transverse-electric (TE 1 ) mode of a PPWG is 27 :

where b represents the plate separation. Substituting Eq. ( 2 ) into Eq. ( 1 ), the phase-matching condition results in an angle-dependent emission frequency:

For an incoming wave, the situation is simply reversed; an incident wave at a given frequency only couples into the waveguide if it arrives at the appropriate angle determined by Eq. ( 3 ). Thus, the design supports both mux and demux capabilities.

Although this initial study of a mux/demux device, and the other device demonstrations mentioned above, all represent significant advances in THz signal processing, it is important to note that these measurements have usually been performed in isolation with an unmodulated continuous-wave or pulsed time-domain source. Characterization of the performance of these devices in the context of a communication system, using data modulated at high bit rate, has for the most part not been demonstrated, and little consideration has yet been given to the enormous challenge of integration into a larger system. Meanwhile, there have also been several recent single-input single-output (SISO) THz link demonstrations 3 , 23 , 32 , 33 , 34 , 35 , which have achieved impressive data rates but have so far not progressed to the integration of any of the aforementioned signal processing components.

In this article, we report an attempt to bridge this conceptual gap, with the characterization of a THz mux/demux subsystem 21 in a real THz data wireless link. We use modulated data to characterize bit error rates and power penalties for this subsystem, as a function of data rate and source power. We achieve single-channel error-free mux/demux at rates up to 10 gigabits per second (Gb/s), as well as the first report of mux/demux of two independent real-time video broadcasts, and the demux of two frequency channels with an aggregate data rate of 50 Gb/s. This work represents the first simultaneous mux/demux of real data flows in the THz range.

Characterization of bit error rate

The numerical simulation in Fig.  1a illustrates the performance of the leaky waveguide in a demux configuration, for a single-frequency (unmodulated) input wave, first propagating inside the waveguide and then radiating into free space and producing a diffracting beam in the far field at an angle determined by Eq. ( 3 ). The solid green and white lines added to this simulation show that the angular spread of first-order modulation sidebands is expected to be smaller than the size of the diffracting carrier wave, even up to 10 Gb/s. This suggests that a detector with sufficient aperture to collect most of the carrier wave will also capture the modulation information required for signal transmission. However, our experimental results, described below, reveal a surprising sensitivity of the signal quality to the angular position of the receiver, resulting from a small angular nonuniformity in the detection sensitivity.

Demultiplexing of modulated THz channels for different data rates. a A 3D numerical simulation (finite element method), of a single-frequency input wave ( f  = 312 GHz) propagating in the waveguide ( b  = 0.733 mm) and then radiating into the far field through a slot in the top plate. The horizontal plane shows the intensity in a plane centered between the metal plates (i.e., inside the waveguide). The vertical (out of plane) arc shows the radiated power as a function of angle. The solid green line indicates the angle predicted by Eq. ( 3 ) for the parameters used in this simulation. The two solid white lines on either side of the green line show the predicted angles for frequencies of 302 GHz and 322 GHz, corresponding to the ±1st-order sidebands for a modulation data rate of 10 Gb/s. The angular spread of these sidebands is smaller than the angular width of the carrier wave diffracting through the slot. b Measured angular distributions for the power ( black curve ) and bit error rate ( BER , red symbols ), for an input frequency of 300 GHz and a modulation rate of 6 Gb/s. Both are normalized to unity and plotted on a log scale (BER plotted as the negative log), to facilitate comparison of the angular widths. c Measured real-time BER performance of the THz link coupled out from the slot, as a function of the angular position of the detector, for a 300 GHz carrier wave. Here, the plate separation b is 0.8 mm and slot width is 0.7 mm. Results for several different data rates all show the same optimum angle of 38.7° independent of the data rates (indicated by the vertical dashed line ), though the angular width varies slightly with data rate. d A model calculation of the effect of a non-uniform angular detection sensitivity on the BER, which qualitatively reproduces the observed results. These curves assume a specific (parabolic) form for the angular detection filter, but otherwise contain no free parameters (see Supplementary Note  1 for details). In this plot, the colors correspond to the same data rates as in ( c )

We first explore the performance of the device in the demux configuration, with a single data-modulated input wave. We generate the THz signal by photomixing two infrared optical signals modulated using an optical modulator, resulting in a an amplitude-modulated signal (amplitude shift keying, ASK) with a carrier frequency determined by the optical frequency difference. This signal is coupled into the waveguide with an input power of about −10 dBm. The waveguide consists of two flat steel plates, with a plate separation of b  = 0.8 mm and a length of 40 mm. The input aperture of the waveguide is tapered to improve the input coupling efficiency 36 . The slot in the top waveguide plate has a length of 28 mm and a width of 0.7 mm, and begins 5 mm beyond the input face of the waveguide. The signal radiated from the slot is collected by a Teflon lens ( f  = 25 mm) and focused onto a Schottky diode receiver. The collection and detection system is mounted on a rotation arm, to characterize the output as a function of the angular position of the receiver. After electrical amplification, the bit error rate (BER) is determined in real-time, i.e., without any off-line processing.

Figure  1 shows typical results for an input wave of 300 GHz (which, for the given value of b , corresponds to an output angle of 38.7°). Figure  1b shows a comparison of the angular distribution of the power to the angular dependence of the BER measured under identical conditions. Figure  1c displays the BER at different receiver angles, for several different data-modulation rates, all with the same carrier frequency.

This figure demonstrates several important results. First, we observe error-free data transmission through the demux device (BER < 10 −10 ) for all data rates, proving that the propagation through the waveguide does not introduce excessive signal loss or distortion due to dispersion. This is consistent with previous work demonstrating the low-loss and low-dispersion characteristics of TE 1 mode propagation in parallel-plate waveguides 27 , 37 . We also note that the optimum BER and maximum power are always obtained at the same angle, regardless of the modulation rate. This is not surprising, as the angle is determined by the carrier frequency and the plate separation, according to Eq. ( 3 ).

The most surprising aspect of Fig.  1b and c involves the angular widths of the BER curves, which are all in the vicinity of just 2 or 3° (FWHM). This is considerably smaller than the measured angular width of the power distribution (as shown clearly in Fig.  1b ), and also smaller than angular aperture of our collection optics. Moreover, at a given BER, the widths of the curves in Fig.  1c vary slightly with data rate, becoming somewhat narrower as the data rate increases. This strong and anomalous angular dependence suggests that the BER is significantly influenced by the angular sensitivity of the detection of modulation sidebands, which co-propagate with the carrier frequency (at slightly different angles, as shown in Fig.  1a ), in a diffraction-limited beam.

Using a simple model for the angular filtering of the receiver, we can qualitatively understand both the observed angular widths and the data-rate dependence shown in Fig.  1c . We imagine that, regardless of the details of the detection system, its sensitivity (when it is located at a particular angular location) is a slowly varying function of the propagation angle of the THz signal, with a maximum sensitivity when the beam propagation angle is equal to the detector angle so that the beam hits the center of the detector. If the detector is moved so that it is not centered on the diffracting beam (i.e., at the angle determined by Eq. ( 3 ) for the carrier frequency), then positive-modulation sidebands and negative-modulation sidebands will not be detected with equal sensitivity. Even if this spectral asymmetry is small, it will lead to a decrease in the overall signal-to-noise of the detection, and thus a degrading of the BER. We note that this effect will not impact the detection of the overall signal power, which explains why the angular width of the power curve is significantly larger than that of the BER curve in Fig.  1b . Modulation at a higher data rate produces sidebands that are more widely spaced in frequency and therefore also in angle. These are more sensitive to the angular filtering as they sample the filter at larger angles away from the optimal central angle. Thus, the angular degradation of the BER is more rapid at higher modulation rates, consistent with our observations. Figure  1d shows the results of a simple model calculation, using an assumed parabolic form for the angular-filter function, which qualitatively reproduce the observed angular widths and also the trend with data rate (see Supplementary Note  1 for details). We note that the BER values estimated from this model change substantially within a small angular range, even though the assumed spectral filter is quite flat, varying by only about 1% within ± 10 GHz of the central frequency.

Given the highly directional nature of THz signals, this angular sensitivity is likely to be a quite general feature of any THz wireless network in which frequency multiplexing is used and in which beam widths are diffraction-limited. This result, which would not have been observed using an unmodulated THz source, has important implication for the trade-off between receiver aperture and data rate, and also for the design of antenna configurations in optimal multiple in/multiple out (MIMO) architectures 3 , 38 .

Another important parameter is the insertion loss, which induces a power penalty for error-free operation. To explore this issue, we compare the measured BER values for demuxed signals (at the optimal receiver angular location) to those measured without demux; in that latter case the detector is placed directly at the location of the demux input port, bypassing the demux waveguide entirely. This result, shown in Fig.  2a , quantifies the power penalty induced by the demux. For example, at 10 Gb/s, the penalty is about 10 dB. These measurements were obtained for a carrier frequency of 312 GHz, and various data rates, up to 10 Gb/s (10 G Ethernet data rate) as indicated in the figure. Insets show the eye diagrams for a modulation rate of 10 Gb/s, both before and after demultiplexing. The eye opening becomes a little bit narrower after demultiplexing due to the power penalty, but it is still possible to obtain error-free transmission at all data rates, reaching a BER below 10 −10 . This penalty is probably due almost entirely to the efficiency of the coupling into and out of the waveguide, and not to propagation losses or dispersion inside the waveguide, which are known to be small 37 .

Demultiplexing of modulated THz channels as a function of detected power. a Measured real-time BER performance of the THz link as a function of the THz power at the receiver under different data rates up to 10 Gb/s. Values are recorded both before the demultiplexer ( left set of curves ), and also after demultiplexing ( right set of curves ) with the detector fixed at the optimum angular position for the carrier frequency of 312 GHz. Data rates are shown next to each curve , in Gb/s. Typical eye diagrams are shown for the input and demultiplexed links at a data rate of 10 Gb/s, both showing error-free transmission ( BER  < 10 −10 ). Before demultiplexing, all the curves have about the same slope. But after the device, the slope changes for the higher data rates (8 and 10 Gb/s), due to scattering of residual radiation at the output end of the waveguide. b One frame from a two-dimensional numerical time-domain simulation movie, depicting the scattering phenomenon, which leads to inter-symbol interference at higher data rates, as discussed in the text. The inset ( upper left ) shows the input waveform for the simulation, which is a 300 GHz carrier wave modulated so that a pulse of radiation enters the waveguide every 100 ps. The waveguide is at the bottom left , where the red arrow indicates the propagation direction for the guided wave. Interference fringes are clearly evident due to interference between the bit emerging from the far end of the waveguide and the previous bit, which radiated through the slot

We also observe that the slope of the demuxed BER curves changes for higher data rates (above 6 Gb/s), indicating an increased noise level at these higher modulation rates. We speculate that this increased noise arises from signals emerging from the far end of the waveguide (rather than from the slot, as intended). The impedance mismatch to free space is not large 39 , so most of the remaining power is emitted into air, and then can scatter from this abrupt waveguide termination to cause interference at the detector. Such scattered signals are delayed by their extra travel time inside the waveguide. If this delay exceeds the duration of a single bit, then this coherent interference can leak over into the subsequent bit, thus degrading the eye diagram. Therefore, one could expect a higher BER for signals with data-modulation rate larger than a certain threshold value determined by the inverse of the extra travel time of the scattered interference signal. The phase delay inside the waveguide, roughly 190 ps, indicates a threshold value near 5 Gb/s for this inter-symbol interference (ISI) effect, which is close to what is observed experimentally in Fig.  2a . This idea is supported by the numerical time-domain simulation shown in Fig.  2b , for a bit period of 100 ps, (corresponding to a data rate of 10 Gb/s). This simulation is somewhat limited in accuracy as it is only a 2D simulation; nevertheless one can clearly see the fringes due to ISI between a bit emerging from the slot and one emerging from the end of the waveguide.

System demonstrations

To demonstrate the real-time mux and demux operation, we use two independent transmitters as shown in the schematic in Fig.  3 . In this case, one channel is the photomixer-based THz source described above, and the other one is a frequency multiplication chain. These two signals with carrier frequencies of 264.7 GHz (channel 1, electronic source) and 322.5 GHz (channel 2, photomixer), are both amplitude-modulated (ASK modulation, as above) with independent bit patterns, both at a data rate of 1.5 Gb/s. The input powers were adjusted to reach a similar performance on the two signals and correspond to around −10 dBm in each channel incident on the mux input. In this case, the waveguide consists of a longer pair of plates (length = 80 mm) with two slots in the top plate, on opposite ends. We use one of the slots to couple two different signals into the waveguide (mux), and the other slot to couple them out (demux). In this measurement, the effective propagation distance for the two signals inside the waveguide is 14 mm. The input angles of the two signals into the first slot are adjusted according to the criterion of Eq. ( 3 ), to optimize the efficiency of input coupling into the waveguide. At the output, the receiver is rotated through a range of angles to characterize the angular distribution of the output, as in Fig.  1 . We measure both the power (Fig.  3c ) and the BER (Fig.  3d ) as a function of angle, for each transmitter individually and also when both signals are in the waveguide at the same time. Figure  3c shows that the optimal output angles are again consistent with the prediction of Eq. ( 3 ). Figure  3d shows that the BER is <10 −10 for both channels, whether or not the other channel is present. In other words, we achieve error-free mux and demux for each channel, whether or not the other channel is simultaneously propagating in the waveguide. The small changes in each BER curve when the other channel is present can be understood by noting the small overlap between the two demuxed beams as show in Fig.  3c . Nevertheless, it is clear that error-free mux-demux can be achieved for both channels. We further demonstrate this remarkable result by modulating the two channels using real video data from two different television broadcasts. When the receiver is rotated from one optimum angular position to another, the received video shown on the monitor switches from one channel (Fig.  3e ) to another (Fig.  3f ).

Schematic diagram and multiplexing/demultiplexing of two THz channels. a Schematic showing the measurement setup, with two different transmitters at 264.7 GHz and 332.5 GHz at fixed angular positions, and with the receiver mounted on a pivoting rail to vary the measurement angle. Power pattern and BER performance for both real-time links at 264.7 GHz and 332.5 GHz are measured after mux-demux with data rate at 1.5 Gb/s. b View of the mux-demux in the experimental setup. c Power pattern measured when channel 1 (264.7 GHz) is on while channel 2 (322.5 GHz) is off ( red curve ), channel 2 is on, whereas channel 1 is off ( blue curve ), and both channels are on ( black curve ). d BER performance for channel 1 only ( red ), channel 2 only ( blue ), channel 1 when channel 2 is on ( light green ) and channel 2 when channel 1 is on ( dark green ). Error-free operation can be achieved in both channels even with both signals on. ( e , f ) Two real-time videos (HD-TV broadcast) transmitted by the two THz links at 264 GHz and 332.5 GHz, each with a data rate of 1.5 Gb/s. The video signals are taken from two different TV broadcast channels and connected to the transmitters. In the monitor connected to the detector, the channel switches when the angular position of the receiver changes. This THz mux/demux can be observed in operation in the  Supplementary Movie , showing excellent stability and reproducibility

Finally, we explore the efficacy of higher order modulation schemes, which can provide increased data rates while using less spectral bandwidth. For this measurement, the photomixer THz source is driven by an optical signal modulated using quadrature phase shift keying (QPSK) at 12.5 Gbaud. In this case, two QPSK-modulated carrier signals, each carrying 25 Gb/s of data, are generated in the photomixer at frequencies of 280 and 330 GHz. These are simultaneously injected into a waveguide in a demux configuration (plate separation = 0.7 mm, slot width = 0.8 mm), and the two outputs were measured independently as a function of angle. To preserve the phase information contained in the QPSK signal, we detect the signals using a sub-harmonic mixer. The down-converted signals are analyzed to recover the constellation diagrams and BER performance for both channels. This result, shown in Fig.  4 , demonstrates demux of two signals with an aggregate data rate of 50 Gb/s, with acceptable BER of ~10 −5 or better for both channels. Although not error-free, the BER is still well below the threshold for forward error correction (typically 2 × 10 −3 ). The degraded BER relative to the results shown in Fig.  3 are probably due to the same effect of interference with scattered light mentioned above, which would be expected to have an increasing impact with increasing data rate.

Demux of two QPSK-modulated channels. BER vs. angle for two channels at 280 GHz and 330 GHz, both modulated at 12.5 Gbaud (corresponding to 25 Gb/s in each channel), for an aggregate throughput of 50 Gb/s. To preserve the QPSK phase information, signals were detected using a Schottky-based sub-harmonic mixer with the output analyzed on a real-time high-bandwidth oscilloscope. In both cases, the optimum BER is well below the threshold for forward error correction. The insets show the constellation diagrams measured for each channel. The vertical dashed lines show the predicted positions of the BER minima for the two channels, according to Eq. ( 3 )

In summary, we have explored the performance of a leaky-wave device for multiplexing and demultiplexing in THz wireless links, using a realistic system configuration with the modulated data. We obtain error-free data transmission through the demux device for all data rates up to 10 Gb/s, which demonstrates that neither insertion loss nor waveguide dispersion are limiting factors in the operation of this mux/demux configuration. We characterize the power penalty when the wave propagates through the waveguide. This effective insertion loss results mainly due to the coupling efficiency between free space and the waveguide mode, and can therefore be further optimized by tailoring the waveguide input and/or the slot width.

Because of the strongly directional and diffraction-limited nature of THz signals, the measured bit error rate depends on the angular location of the detector, which changes with the data-modulation rate. This new phenomenon can be understood by applying a relatively simple filtering model. As any network operating above 100 GHz is almost certain to exhibit narrow diffraction-limited beams, this may be the limiting factor in achievable data rate, for a given single-point receiver aperture. On the other hand, in a MIMO configuration different antennas in an array may receive different subsets of the total spectral information in a signal. This presents an interesting challenge in the optimal detection and demodulation of demuxed signals, which could overcome the limitation imposed by a diffracting beam with spectral sidebands.

In addition, we demonstrate the effectiveness of this mux/demux approach by operating two independent wireless links at 264.7 GHz and 332.5 GHz to demonstrate real-time mux and demux, for simultaneous error-free transmission of two video signals with ASK modulation, as well as the demux of two QPSK-modulated signals with aggregate data rate of 50 Gb/s. Our results clearly suggest that two frequency channels is not the limit; additional channels could be added for increased aggregate throughput. In our earlier work 21 , we modeled a six-channel configuration with equal 20 GHz-wide channels spaced over 150 GHz of spectrum. This model configuration seems to be feasible, although an experimental realization would require an array of sources that are probably not yet available in any one laboratory. The practical limit on channel number will likely be determined by the size and positioning of coupling optics. We note that this mux/demux configuration can also accommodate mobility, with continuous tuning of the carrier frequency as a user moves and the angle between the waveguide axis and the user changes. This would obviously require a continuously tunable or very broadband THz source, which may be feasible using SiGe BiCMOS process technology 40 .

It is interesting to note the contrast with free-space optical (FSO) networking, another feasible approach to achieving wireless links with Tb/s throughput. FSO links can also employ frequency multiplexing, and like a THz link, the signals propagate as directional beams, not omnidirectional broadcasts 41 . However, the wavelength-dependent diffraction effects described here would not be expected to manifest themselves in FSO systems. The relevant parameter here, to determine the significance of diffraction effects, is the spacing between adjacent frequency channels d v , as a fraction of the average carrier frequency v 0 . In a typical frequency-multiplexed FSO system 41 , this fractional spacing d v / v 0 is quite small, on the order of 10 −4 . In contrast, for our system demonstration (Fig.  4 ), this parameter is almost three orders of magnitude larger. Thus, diffractive spreading of the carrier wave (and all modulation sidebands) is a significant phenomenon in THz systems, and is irrelevant in FSO links where all of the multiplexed signals co-propagate with parallel wave vectors. Beam diffraction can be both a challenge and an advantage; for example, beam misalignment due to, e.g., atmospheric turbulence is a huge challenge for long-distance FSO links with tightly collimated beams, but has essentially no impact on THz links 42 . Of course, THz links also afford the substantial advantage that coherent phase-sensitive detection is relatively straightforward, which enables MIMO architectures that would be exceedingly challenging to implement using visible or near-infrared light sources.

Finally, by noting the differences between simple power measurements and BER data, we emphasize the fact that the study of THz signal processing devices using modulated data in realistic configurations can reveal new information about their characteristics. In many cases including this one, this information cannot be readily obtained using conventional measurements with an unmodulated continuous-wave or pulsed time-domain source. Thus, measurements using data-modulated signals will be crucial for optimizing device performance in communication networks.

Measurement setup

The THz link performance measurement setup consists of two THz sources, one based on photomixing technologies (332.5 GHz) and the other on a frequency multiplexer chain (264.7 GHz) with a tunable output in the 260–330 GHz frequency band. Detection is achieved using a zero-biased Schottky diode broadband intensity detector associated to RF amplifiers (amplification bandwidth of 12 GHz, which determines the overall system bandwidth) to drive the BER tester (N4903A J-BERT from Agilent Technologies, with the option A01/C13). The average output power of the two THz sources is tunable and adjusted to reach the best driving signal for the Schottky diode and RF detection for BER measurements. We verified that the two beams contain almost same power, by comparing the rectified voltages at Schottky output at the two optimal angles. For the THz signal intensity detection investigated in this study, we keep the THz power low enough to avoid saturating the detector, to optimize the signal-to-noise ratio of the detected signals. Last, we use absorbers to prevent detection of spurious signals that could leak out of the far end of the waveguide and scatter towards the receiver, or that could couple from the source directly to the receiver without propagating through the waveguide. We found that these absorbers were necessary in order to measure error-free performance, due to the effects of scattered radiation. Indeed, our efforts to block scattered signal at the waveguide output may require further improvement, as suggested by the data of Fig.  2 . This emphasizes the extreme sensitivity of the BER to interference from scattered signals, which must be addressed with some care.

For the experiments employing QPSK modulation, an optical signal is modulated using a dual-nested Mach-Zender modulator before the photomixing process to generate the dual THz signal at 280 and 330 GHz. Two arbitrary waveform generators are used to create two baseband non-return-to-zero (NRZ) data signals for the in-phase and quadrature date flows. For detection, the dual frequency THz signal is down-converted in a Schottky-based sub-harmonic mixer to below 40 GHz. The output is amplified and then detected by a wide bandwidth oscilloscope (Tektronix DPO70000SX ATI, bandwidth of 70 GHz). The two QPSK signals corresponding to the two down-converted THz channels are analyzed to recover the two 25 Gb/s modulated data and the corresponding constellation diagrams.

Simulations

Finite element method (FEM) simulation results were performed using COMSOL Multiphysics 5.2 with the RF module. Figure  1a shows a typical simulation result. For this figure, a perfect electric conductor (PEC) was used for the waveguide boundaries, with perfectly matched layers (PML) to absorb at the waveguide output. Scattering boundaries were used on the waveguide edges and on the upper air boundaries. A port boundary was used for the waveguide incidence, exciting the TE 1 mode with a spot size of 1 mm. The waveguide width and length were 25 mm, with a 0.733 mm plate separation. The waveguide slot is 0.7 mm in width and 3 mm long and is located 4 mm from the front of the waveguide. The air above the waveguide is a 60° circle section extrusion with a radius of 22 mm and a width of 3 mm. Tetrahedral elements were used to mesh the geometry with a total of 4,831,496 domain elements. This simulation was solved at 312 GHz using the GMRES iterative solver.

The result shown in Fig.  2b was obtained using COMSOL Multiphysics 5.2 with the RF module in a transient finite difference time-domain simulation. PEC was used for the waveguide boundaries, with scattering boundary conditions to absorb in free space. A scattering boundary is used for the waveguide input. For exciting the parallel-plate waveguide TE 1 mode, an amplitude-modulated signal was used as the input with a carrier frequency of 300 GHz, and with a modulation corresponding to a 10 Gbps data rate. The waveguide length was 33 mm, with a 0.8 mm plate separation. The waveguide slot is 3 mm long and is located 1 mm from the front of the waveguide. The air above the waveguide is a 60° circle section with a radius of 66 mm and a sector angle of 70°. Tetrahedral elements were used to mesh the geometry with a total of 465,048 domain elements. The simulation was solved to 300 ps with 0.1 ps time resolution.

Data availability

All relevant data are available from the authors.

Cisco VNI Mobile Forecast. http://www.cisco.com/c/en/us/solutions/collateral/service-provider/visual-networking-index-vni/mobile-white-paper-c11-520862.pdf . (2015–2020)

Federici, J. & Moeller, L. Review of terahertz and subterahertz wireless communications. J. Appl. Phys. 107 , 111101 (2010).

Article   ADS   Google Scholar  

Kleine-Ostmann, T. & Nagatsuma, T. A review on terahertz communications research. J. Infrared Millim. Terahertz Waves 32 , 143–171 (2011).

Article   Google Scholar  

Kürner, T. & Priebe, S. Towards THz communications—status in research, standardization, and regulation. J. Infrared Millim. Terahertz Waves 35 , 53–62 (2014).

Nagatsuma, T., Ducournau, G. & Renaud, C. C. Advances in terahertz communications accelerated by photonics. Nat. Photonics 10 , 371–379 (2016).

Article   CAS   ADS   Google Scholar  

Kersting, R., Strasser, G. & Unterrainer, K. Terahertz phase modulator. Electron Lett. 36 , 1156–1158 (2000).

Chen, H.-T. et al. A metamaterial solid-state terahertz phase modulator. Nat. Photonics 3 , 141–151 (2009).

ADS   Google Scholar  

Sensale-Rodriguez, B. et al. Broadband graphene terahertz modulators enabled by intraband transitions. Nat. Commun. 3 , 780 (2012).

Article   PubMed   Google Scholar  

Karl, N. J. et al. An electrically driven terahertz metamaterial diffraction modulator with over 20 dB of dynamic range. Appl. Phys. Lett. 104 , 091115 (2014).

Meijer, A. S. et al. An ultrawide-bandwidth single-sideband modulator for terahertz frequencies. Nat. Photonics 10 , 740–744 (2016).

Pandey, S., Kumar, G. & Nahata, A. Slot waveguide-based splitters for broadband terahertz radiation. Opt. Express 18 , 23466–23471 (2010).

Article   PubMed   ADS   Google Scholar  

Reichel, K., Mendis, R. & Mittleman, D. M. A broadband terahertz waveguide T-junction variable power splitter. Sci. Rep. 6 , 28925 (2016).

Article   CAS   PubMed   PubMed Central   ADS   Google Scholar  

Libon, I. H. et al. An optically controllable terahertz filter. Appl. Phys. Lett. 76 , 2821–2823 (2000).

Chen, C.-Y., Pan, C.-L., Hsieh, C.-F., Lin, Y.-F. & Pan, R.-P. Liquid-crystal-based terahertz tunable Lyot filter. Appl. Phys. Lett. 88 , 101107 (2006).

Chen, C.-Y., Hsieh, C.-F., Lin, Y.-F., Pan, R.-P. & Pan, C.-L. Magnetically tunable room-temperature 2p liquid crystal terahertz phase shifter. Opt. Express 12 , 2625–2630 (2004).

Sengupta, K. & Hajimiri, A. A 0.28 THz power-generatoin and beam-steering array in CMOS based on distributed active radiators. IEEE J. Solid-State Circ. 47 , 3013–3031 (2012).

Monnai, Y. et al. Terahertz beam steering and variable focusing using programmable diffraction gratings. Opt. Express 21 , 2347–2354 (2013).

Hashemi, M. R. M., Yang, S.-H., Wang, T., Sepulveda, N. & Jarrahi, M. Electronically-controlled beam-steering through vanadium dioxide metasurfaces. Sci. Rep. 6 , 35439 (2016).

Krumbholz, N. et al. Omnidirectional terahertz mirrors: a key element for future terahertz communication systems. Appl. Phys. Lett. 88 , 202905 (2006).

Ibraheem, I. A., Krumbholz, N., Mittleman, D. M. & Koch, M. Low dispersive dielectric mirrors for future terahertz wireless communication systems. IEEE Microwave Wireless Comp. Lett. 18 , 67–69 (2008).

Karl, N. J., McKinney, R. W., Monnai, Y., Mendis, R. & Mittleman, D. M. Frequency-division multiplexing in the terahertz range using a leaky-wave antenna. Nat. Photonics 9 , 717–720 (2015).

Yata, M., Fujita, M. & Nagatsuma, T. Photonic crystal diplexers for terahertz-wave applications. Opt. Express 24 , 7835–7849 (2016).

Article   CAS   PubMed   ADS   Google Scholar  

Jia, S. et al. THz photonic wireless links with 16-QAM modulation in the 375-450 GHz band. Opt. Express 24 , 23777–23783 (2016).

Yang, Y., Shutler, A. & Grischkowsky, D. Measurement of the transmission of the atmosphere from 0.2 to 2 THz. Opt. Express 19 , 8830–8838 (2011).

Proposal for IEEE802.15.3d—THz PHY. https://mentor.ieee.org/802.15/dcn/16/15-16-0595-03-003d-proposal-for-ieee802-15-3d-thz-phy.docx .

Haider, M. K. & Knightly, E. W. Mobility resilience and overhead constrained adaptation in directional 60 GHz WLANs: protocol design and system implementation. In Proceedings of the 17th International Symposium on Mobile Ad Hoc Networking and Computing 61–70 (ACM, 2016).

Mendis, R. & Mittleman, D. M. Comparison of the lowest-order transverse electric (TE 1 ) and transverse magnetic (TEM) modes of the parallel-plate waveguide for terahertz pulse applications. Opt. Express 17 , 14839–14850 (2009).

Mendis, R. & Mittleman, D. M. An investigation of the lowest-order transverse electric (TE 1 ) mode of the parallel-plate waveguide for THz pulse propagation. J. Opt. Soc. Am. B 26 , 6–13 (2009).

Balanis, C. A. Modern Antenna Handbook (Wiley, 2011).

Monnai, Y. et al. Terahertz beam focusing based on plasmonic waveguide scattering. Appl. Phys. Lett. 101 , 015116 (2012).

McKinney, R. W., Monnai, Y., Mendis, R. & Mittleman, D. M. Focused terahertz waves generated by a phase velocity gradient in a parallel-plate waveguide. Opt. Express 23 , 27947–27952 (2015).

Koenig, S. et al. Wireless sub-THz communication system with high data rate. Nat. Photonics 7 , 977–981 (2013).

Nagatsuma, T. et al. Terahertz wireless communications based on photonics technologies. Opt. Express 21 , 23736–23747 (2013).

Ducournau, G. et al. THz communications using photonics and electronic devices: the race to data-rate. J. Infrared Millim. Terahertz Waves 36 , 198–220 (2015).

Kanno, A. et al. Coherent terahertz wireless signal transmission using advanced optical fiber communication technology. J. Infrared Millim. Terahertz Waves 36 , 180–197 (2015).

Gerhard, M., Theuer, M. & Beigang, R. Coupling into tapered metal parallel plate waveguides using a focused terahertz beam. Appl. Phys. Lett. 101 , 041109 (2012).

Mbonye, M., Mendis, R. & Mittleman, D. M. Inhibiting the TE1-mode diffraction losses in terahertz parallel plate waveguides using concave plates. Opt. Express 20 , 27800–27809 (2012).

Akyildiz, I. F. & Jornet, J. M. Realizing ultra-massive MIMO (1024 × 1024) communication in the (0.06-10) terahertz band. Nano Commun. Netw. 8 , 46–54 (2016).

Mbonye, M., Mendis, R. & Mittleman, D. M. Study of the impedance mismatch at the output end of a THz parallel-plate waveguide. Appl. Phys. Lett. 100 , 111120 (2012).

Chen, P. Y., Assefzadeh, M. M. & Babakhani, A. A nonlinear Q-switching impedance technique for picosecond pulse radiation in silicon. IEEE Trans. Microwave Theory Tech. 64 , 4685–4700 (2016).

Lin, C.-Y. et al. A 400 Gbps/100 m free-space optical link. Laser Phys. Lett. 14 , 025206 (2017).

Ma, J., Moeller, L. & Federici, J. F. Experimental comparison of terahertz and infrared signaling in controlled atmospheric turbulence. J. Infrared Millim. Terahertz Waves 36 , 130–143 (2015).

Download references

Acknowledgements

This work was supported by the US National Science Foundation, the US Army Research Office, and the W.M. Keck Foundation. The experimental setup of the THz communication was supported by the Agence Nationale de la Recherche (ANR) for funding the COM’TONIQ “Infra” 2013 program on THz communications, through the Grant ANR-13-INFR-0011-01 and the TERALINKS Chist-era project (Grant ANR-16-CHR2-0006-01), and the support from several French research programs and institutes—Lille University, IEMN institute (RF/MEMS Characterization Center, Nanofab and Telecom platform), IRCICA institute (USR CNRS 3380), the CNRS and by the French RENATECH network. This work was also supported in part by the French Programmes d’investissement d’avenir Equipex FLUX 0017, ExCELSiOR project and the Nord-Pas de Calais Regional council, and the FEDER through the CPER Photonics for Society, and the support of Tektronix (Klaus Engenhardt and Erwan Lecomte) considering the hardware used for QPSK measurements (AWG, optical modulation, and ATI 70 GHz Oscilloscope for wide bandwidth analysis). We also acknowledge valuable conversations with Prof. Larry Larson and Prof. Christopher Rose, both of Brown University.

Author information

Authors and affiliations.

School of Engineering, Brown University, 184 Hope Street, Providence, RI, 02912, USA

Jianjun Ma, Nicholas J. Karl & Daniel M. Mittleman

Institut d’Electronique de Microélectronique et de Nanotechnologie (IEMN), UMR CNRS 8520, Université de Lille 1, 59652, Villeneuve d’Ascq Cedex, France

Sara Bretin & Guillaume Ducournau

You can also search for this author in PubMed   Google Scholar

Contributions

All of the authors concieved of the experiments, and contributed to their design. J.M., S.B., and G.D. performed the measurements. N.J.K. performed the numerical simulations. All of the authors contributed to writing the manuscript.

Corresponding author

Correspondence to Daniel M. Mittleman .

Ethics declarations

Competing interests.

The authors declare no competing financial interests.

Additional information

Publisher's note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Electronic supplementary material

Supplementary information, description of additional supplementary files, supplementary movie 1, rights and permissions.

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/ .

Reprints and permissions

About this article

Cite this article.

Ma, J., Karl, N.J., Bretin, S. et al. Frequency-division multiplexer and demultiplexer for terahertz wireless links. Nat Commun 8 , 729 (2017). https://doi.org/10.1038/s41467-017-00877-x

Download citation

Received : 06 March 2017

Accepted : 29 July 2017

Published : 28 September 2017

DOI : https://doi.org/10.1038/s41467-017-00877-x

Share this article

Anyone you share the following link with will be able to read this content:

Sorry, a shareable link is not currently available for this article.

Provided by the Springer Nature SharedIt content-sharing initiative

This article is cited by

Wireless communications sensing and security above 100 ghz.

• Josep M. Jornet
• Edward W. Knightly
• Daniel M. Mittleman

Nature Communications (2023)

Conformal leaky-wave antennas for wireless terahertz communications

• Hichem Guerboukha
• Rabi Shrestha

Communications Engineering (2023)

Terahertz Beam Steering: from Fundamentals to Applications

• Yasuaki Monnai
• Kaushik Sengupta

Journal of Infrared, Millimeter, and Terahertz Waves (2023)

Topology optimization of microwave frequency dividing multiplexers

• Ahmad H. Bokhari
• Emadeldeen Hassan
• Eddie Wadbro

Structural and Multidisciplinary Optimization (2023)

• Priyangshu Sen
• Jose V. Siles

Nature Electronics (2022)

By submitting a comment you agree to abide by our Terms and Community Guidelines . If you find something abusive or that does not comply with our terms or guidelines please flag it as inappropriate.

Quick links

• Explore articles by subject
• Guide to authors
• Editorial policies

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

• Digital Electronics Tutorial
• Digital Electronics - Home
• Digital Electronics Basics
• Types of Digital Systems
• Types of Signals
• Logic Levels And Pulse Waveforms
• Digital System Components
• Digital Logic Operations
• Digital Systems Advantages
• Number Systems
• Base Conversions
• Binary Numbers Representation
• Binary Arithmetic
• Signed Binary Arithmetic
• Octal Arithmetic
• Hexadecimal Arithmetic
• Complement Arithmetic
• Binary Codes
• 8421 BCD Code
• Excess-3 Code
• ASCII Codes
• EBCDIC Code
• Code Conversion
• Error Detection & Correction Codes
• Logic Gates
• Universal Gates
• CMOS Logic Gate
• Two Level Logic Realization
• Threshold Logic
• Boolean Algebra
• Laws of Boolean Algebra
• Boolean Functions
• DeMorgan's Theorem
• SOP and POS Form
• Minimization Techniques
• K-Map Minimization
• Three Variable K-Map
• Four Variable K-Map
• Five Variable K-Map
• Six Variable K-Map
• Don't Care Condition
• Quine-McCluskey Method
• Min Terms and Max Terms
• Canonical and Standard Form
• Max Term Representation
• Simplification using Boolean Algebra
• Combinational Logic Circuits
• Digital Combinational Circuits
• Digital Arithmetic Circuits
• Multiplexers
• Parity Bit Generator and Checker
• Comparators
• Keyboard Encoders
• Priority Encoders
• Demultiplexers
• Arithmetic Logic Unit
• 7-Segment LED Display
• Code Converters
• Binary to Decimal Converter
• Decimal to BCD Converter
• BCD to Decimal Converter
• Binary to Gray Code Converter
• Gray Code to Binary Converter
• BCD to Excess-3 Converter
• Excess-3 to BCD Converter
• Half Adders
• Full Adders
• Serial Adders
• Parallel Adders
• Full Adder using Half Adder
• Half Adder vs Full Adder
• Binary Adder-Subtractor
• Subtractors
• Half Subtractors
• Full Subtractors
• Parallel Subtractors
• Full Subtractor using 2 Half Subtractors
• Half Subtractor using NAND Gates
• Sequential Logic Circuits
• Digital Sequential Circuits
• Clock Signal and Triggering
• Conversion of Flip-Flops
• Shift Registers
• Shift Register Applications
• Finite State Machines
• Algorithmic State Machines
• A/D and D/A Converters
• Analog-to-Digital Converter
• Digital-to-Analog Converter
• DAC and ADC ICs
• Realization of Logic Gates
• NOT Gate from NAND Gate
• OR Gate from NAND Gate
• AND Gate from NAND Gate
• NOR Gate from NAND Gate
• XOR Gate from NAND Gate
• XNOR Gate from NAND Gate
• NOT Gate from NOR Gate
• OR Gate from NOR Gate
• AND Gate from NOR Gate
• NAND Gate from NOR Gate
• XOR Gate from NOR Gate
• XNOR Gate from NOR Gate
• NAND/NOR Gate using CMOS
• Memory Devices
• RAM and ROM
• Cache Memory Design
• Programmable Logic Devices
• Programmable Logic Array
• Programmable Array Logic
• Field Programmable Gate Arrays
• Digital Electronics Families
• CPU Architecture
• Digital Electronics Useful Resources
• Digital Electronics - Quick Guide
• Digital Electronics - Resources
• Digital Electronics - Discussion
• Selected Reading
• UPSC IAS Exams Notes
• Developer's Best Practices
• Questions and Answers
• Effective Resume Writing
• HR Interview Questions
• Computer Glossary

Digital Electronics - Demultiplexers

What is a demultiplexer.

A Demultiplexer is a combinational logic circuit that accepts a single input and distributes it over several output lines. Demultiplexer is also termed as DEMUX in short. As Demultiplexer is used to transmit the same data to different destinations, hence it is also known as data distributor .

There is another combinational logic circuit named multiplexer which performs opposite operation of the Demultiplexer, i.e. accepts several inputs and transmits one of them at time to the output line.

From the definition, we can state that a Demultiplexer is a 1-to-2 n device. The functional block diagram of a typical 1×2 n Demultiplexer is shown in Figure-1.

It can be seen that the Demultiplexer has only one data input line, 2 n output lines, and n select lines. The logic level applied to select lines of the Demultiplexer determines the output channel to which the input data will be transmitted.

Demultiplexer circuit are the combinational logic circuit widely used in digital decoders and Boolean function generator circuits.

Types of Demultiplexer

Based on the number of output lines (2 n ), Demultiplexers can be classified into several types. Some commonly used types of Demultiplexers are −

1×2 Demultiplexer

1×4 demultiplexer.

Now, let us briefly discuss each type of Demultiplexer.

The functional block diagram of a 1×2 Demultiplexer is shown in Figure-2.

The 1×2 Demultiplexer consists of 1 input line (I), 1 select line (S), and 2 output lines (Y 0 and Y 1 ). The logic level applied at the select line determines the output line to which the input data will be transmitted.

The operation of the 1×2 Demultiplexer can be analyzed with the help of its function table given below.

From this function table of 1×2 Demultiplexer, we can directly derive the Boolean expression for each output as follow.

$$\mathrm{Y_{0} \: = \: \bar{S} \: I}$$

$$\mathrm{Y_{1} \: = \: S \: I}$$

The functional block diagram of 1×4 Demultiplexer is shown in Figure-3.

The 1×4 Demultiplexer has 1 input line (I), 2 select line (S 0 and S 1 ), and 4 output lines (Y 0 , Y 1 , Y 2 , and Y 3 ). The logic level applied to the select lines determines the output line to which the input data (I) will be transmitted.

The operation of the 1×4 Demultiplexer can be understood with the help of its function table given below.

From this truth table of 1×4 Demultiplexer, we can directly write the Boolean expression for each output as follow.

$$\mathrm{Y_{0} \: = \: \bar{S_{1}} \: \bar{S_{0}} \: I}$$

$$\mathrm{Y_{1} \: = \: \bar{S_{1}} \: S_{0} \: I}$$

$$\mathrm{Y_{2} \: = \: S_{1} \: \bar{S_{0}} \: I}$$

$$\mathrm{Y_{3} \: = \: S_{1} \: S_{0} \: I}$$

We can easily understand the operation of the above circuit. Similarly, you can implement 1×8 Demultiplexer and 1×16 Demultiplexer by following the same procedure.

Implementation of Higher-order Demultiplexer

Now, let us implement the following two higher-order Demultiplexers using lower-order Demultiplexers.

• 1×8 Demultiplexer

1×16 Demultiplexer

1×8 deultiplexer.

In this section, let us implement 1×8 Demultiplexer using 1×4 Demultiplexers and 1×2 Demultiplexer. We know that 1×4 Demultiplexer has single input, two selection lines and four outputs. Whereas, 1×8 Demultiplexer has single input, three selection lines and eight outputs.

So, we require two 1×4 Demultiplexers in second stage in order to get the final eight outputs. Since, the number of inputs in second stage is two, we require 1×2 Demultiplexer in first stage so that the outputs of first stage will be the inputs of second stage. Input of this 1×2 Demultiplexer will be the overall input of 1×8 Demultiplexer.

Let the 1×8 Demultiplexer has one input I, three selection lines s 2 , s 1 & s 0 and outputs Y 7 to Y 0 . The Truth table of 1×8 Demultiplexer is shown below.

We can implement 1×8 Demultiplexer using lower order Multiplexers easily by considering the above Truth table. The block diagram of 1×8 Demultiplexer is shown in the following figure.

The common selection lines, s 1 & s 0 are applied to both 1×4 Demultiplexers. The outputs of upper 1×4 Demultiplexer are Y 7 to Y 4 and the outputs of lower 1×4 Demultiplexer are Y 3 to Y 0 .

The other selection line, s 2 is applied to 1×2 Demultiplexer. If s 2 is zero, then one of the four outputs of lower 1×4 Demultiplexer will be equal to input, I based on the values of selection lines s 1 & s 0 . Similarly, if s 2 is one, then one of the four outputs of upper 1×4 Demultiplexer will be equal to input, I based on the values of selection lines s 1 & s 0 .

In this section, let us implement 1×16 Demultiplexer using 1×8 Demultiplexers and 1×2 Demultiplexer. We know that 1×8 Demultiplexer has single input, three selection lines and eight outputs. Whereas, 1×16 Demultiplexer has single input, four selection lines and sixteen outputs.

So, we require two 1×8 Demultiplexers in second stage in order to get the final sixteen outputs. Since, the number of inputs in second stage is two, we require 1×2 Demultiplexer in first stage so that the outputs of first stage will be the inputs of second stage. Input of this 1×2 Demultiplexer will be the overall input of 1×16 Demultiplexer.

Let the 1×16 Demultiplexer has one input I, four selection lines s 3 , s 2 , s 1 & s 0 and outputs Y 15 to Y 0 . The block diagram of 1×16 Demultiplexer using lower order Multiplexers is shown in the following figure.

The common selection lines s 2 , s 1 & s 0 are applied to both 1×8 Demultiplexers. The outputs of upper 1×8 Demultiplexer are Y 15 to Y 8 and the outputs of lower 1×8 Demultiplexer are Y 7 to Y 0 .

The other selection line, s 3 is applied to 1×2 Demultiplexer. If s 3 is zero, then one of the eight outputs of lower 1×8 Demultiplexer will be equal to input, I based on the values of selection lines s 2 , s 1 & s 0 . Similarly, if s3 is one, then one of the 8 outputs of upper 1×8 Demultiplexer will be equal to input, I based on the values of selection lines s 2 , s 1 & s 0 .

Integrated Circuits (ICs) Working as Demultiplexer

Demultiplexer can also be built in the form of ICs. There are several types of ICs available that work as Demultiplexer. Some common of them are listed below −

• 74139 IC works as a 1×4 Demultiplexer
• 74237 IC works as a 1×8 Demultiplexer
• 74154 IC works as a 1×16 Demultiplexer

Advantages of Demultiplexer

The important advantages of Demultiplexer are given below −

• By using Demultiplexers, we can increase the efficiency of the communication systems.
• Demultiplexer can separate different signals from a mixed signal stream.
• Demultiplexer can decode the signals produced by a multiplexer.

Disadvantages of Demultiplexer

The major disadvantages of Demultiplexers are listed below −

• The use of Demultiplexer can cause wastage of bandwidth.
• The synchronization of signals can create a delay in the system.

Applications of Demultiplexer

Demultiplexer is a crucial combinational logic circuit which is used in a number of applications. Some important uses of Demultiplexers are listed below −

• Demultiplexer are used in several input and output devices for data routing.
• Demultiplexer are used in digital control systems to select one signal from a mutual stream of signals.
• Demultiplexer are also employed for data transmission in synchronous systems.
• Demultiplexer are also utilized in data acquisition systems.
• Demultiplexer can be used for generating Boolean functions.
• Demultiplexer can be used in serial to parallel converters.
• Demultiplexer are used for broadcasting of ATM packets.
• Demultiplexer can also be used to design automatic test equipment, etc.

This is all about Demultiplexer, its types, and applications.

• Combinational Logic Cirucits , Most Popular

Multiplexer (MUX) And Multiplexing (2 to 1, 4 to 1, 8 to 1 & 16 to 1)

• August 9, 2024
• By Ravi Teja

Imagine sending HD video, music, emails, phone calls, and internet all down one wire! Multiplexing is the magic trick, and multiplexers (MUX for short) are the tiny wizards behind it. In this guide, learn what is a Multiplexer, different types of multiplexers like 2 to 1, 4 to 1, 8 to 1 and 16 to 1 Multiplexer, commonly available Multiplexer ICs and some important applications of Multiplexers.

What Is Multiplexing?

Multiplexing is the process of combining one or more signals and transmitting on a single channel. In analog communication systems, a communication channel is a scarce quantity, which must be properly used. For cost-effective and efficient use of a channel, the concept of Multiplexing is very useful as it allows multiple users to share a single channel in a logical way.

The three common Types of Multiplexing approaches are:

Two of the best examples of Multiplexing Systems used in our day-to-day life are the landline telephone network and the Cable TV.

The device which is responsible for Multiplexing is known as Multiplexer. Multiplexers are used for both Analog and Digital signals. Let us focus on digital signals in this tutorial, to keep things simple. A multiplexer is the most frequently used combinational circuit and it is an important building block in many in digital systems.

These are mostly used to form a selected path between multiple sources and a single destination. A basic multiplexer has various data input lines and a single output line. These are found in many digital system applications such as data selection and data routing, logic function generators, digital counters with multiplexed displays, telephone network, communication systems, waveform generators, etc. In this article we are going to discuss about types of multiplexers and its design.

What Is A Multiplexer?

The multiplexer or MUX is a digital switch, also called as data selector. It is a Combinational Logic Circuit with more than one input line, one output line and more than one select line. It accepts the binary information from several input lines or sources and depending on the set of select lines, a particular input line is routed onto a single output line.

The basic idea of multiplexing is shown in figure below in which data from several sources are routed to the single output line when the enable switch is ON. This is why, multiplexers are also called as ‘many to one’ combinational circuits.

The below figure shows the block diagram of a multiplexer consisting of n input lines, m selection lines and one output line. If there are m selection lines, then the number of possible input lines is 2 m . Alternatively, we can say that if the number of input lines is equal to 2 m , then m selection lines are required to select one of n (consider 2 m = n) input lines.

This type of multiplexer is referred to as 2 n × 1 multiplexer or 2 n -to-1 multiplexer. For example, if the number of input lines is 4, then two select lines are required. Similarly, to select one of 8 input lines, three select lines are required.

Generally, the number of data inputs to a multiplexer is a power of two such as 2, 4, 8, 16, etc. Some of the most frequently used multiplexers include 2-to-1, 4-to-1, 8-to-1 and 16-to-1 multiplexers.

These multiplexers are available in IC forms with different input and select line configurations. Some of the available multiplexer ICs include 74157 (Quad 2-to-1 MUX), 78158 (Quad 2-to-1 MUX with inverse output), 74153 (4-to-1 MUX), 74152 (8-to-1 MUX) and 74150 (16-to-1 MUX).

Also Read: What Is A Demultiplexer

2 to1 Multiplexer

A 2 to 1 multiplexer consists of two inputs D0 and D1, one select input S and one output Y. Depending on the select signal, the output is connected to either of the inputs. Since there are two input signals, only two ways are possible to connect the inputs to the outputs, so one select is needed to do these operations.

If the select line is low, then the output will be switched to D0 input, whereas if select line is high, then the output will be switched to D1 input. The figure below shows the block diagram of a 2:1 mux which connects two 1-bit inputs to a common destination.

2×1 Multiplexer Calculator

2×1 multiplexer truth table is shown below. Depending on the value of the select input, the inputs i.e., D0, D1 are produced at outputs. The output is D0 when Select value is S = 0 and the output is D1 when Select value is S = 1.

‘X’ in the above 2:1 multiplexer truth table denotes a don’t care condition. So, ignoring the don’t care conditions, we can derive the MUX Boolean Expression of a typical 2:1 Multiplexer as follows:

From the above output expression, the logic circuit of 2-to-1 multiplexer can be implemented using logic gates as shown in figure. It consists of two AND gates, one NOT gate and one OR gate. When the select line, S=0, the output of the lower AND gate is zero, but the output of upper AND gate is D0. Thus, the output generated by the OR gate is equal to D0.

Similarly, when S=1, the output of the upper AND gate is zero, but the output of lower AND gate is D1. Therefore, the output of the OR gate is D1. Thus, the above given mux Boolean expression is satisfied by this circuit.

In order to efficiently use the Silicon, IC Manufacturers fabricate multiple Multiplexers in a single IC. Generally four 2 line to 1 line multiplexers are fabricated in a single IC. Some of the popular ICs of 2 to 1 multiplexers include IC 74157 and IC 74158.

Both these ICs are Quad 2-to-1 Multiplexers. While IC 74157 has a normal output, the IC74158 has an inverted output. There is only one selection line, which controls the input lines to the output in all four multiplexers.

The output Y0 can be either A0 or B0 depending on the status of the select line. Similarly, Y1 can be either A1 or B1, Y2 can be either A2 or B2 and so on. There is an additional Strobe or Enable control input E/Strobe, which enables and disables all the multiplexers, i.e., when E=1, outputs of all the multiplexer is zero irrespective of the value of S.

All the multiplexers are activated only when the E / Strobe input is LOW.

4 to 1 Multiplexer

A  4 to 1 multiplexer consists four data input lines as D0 to D3, two select lines as S0 and S1 and a single output line Y. The select lines S0 and S1 select one of the four input lines to connect the output line. The figure below shows the block diagram of a 4:1 multiplexer in which, the multiplexer decodes the input through select line.

4×1 Multiplexer Calculator

The 4×1 multiplexer truth table is shown below in which four input combinations 00, 10, 01 and 11 on the select lines respectively switches the inputs D0, D2, D1 and D3 to the output. That means when S0=0 and S1 =0, the output at Y is D0, similarly Y is D1 if the select inputs S0=0 and S1= 1 and so on.

From the above 4:1 multiplexer truth table, we can write the output expressions as follows:

From the above expression of the output, a 4-to-1 multiplexer can be implemented by using basic logic gates. The below figure shows the logic circuit of 4:1 MUX which is implemented by four 3-inputs AND gates, two 1-input NOT gates, and one 4-inputs OR gate.

In this circuit, each data input line is connected as input to an AND gate and two select lines are connected as other two inputs to it. Additionally, there is also an Enable Signal. The output of all the AND gates are connected to inputs of OR gate in order to produce the output Y.

Generally, this type of multiplexers is available in IC with dual mode i.e., there will be two 4-to-1 Multiplexers in a single IC. The most common and popular 4-to-1 line multiplexer is IC 74153 which, is a dual 4-to-1 line multiplexer. It consists of two identical 4-to-1 multiplexers. It has two separate enable or strobe inputs to switch ON or OFF the individual multiplexers. But the Select lines are common to both the Multiplexers.

Usually, the enable input or strobe can be used to cascade two or more multiplexer ICs to construct a multiplexer with large number of inputs. Each multiplier is supplied with separate inputs. The figure below shows the pin diagram of IC74153.

8 to 1 Multiplexer

An 8 to 1 multiplexer consists of eight data inputs D0 through D7, three input select lines S0 through S2 and a single output line Y. Depending on the select lines combinations, multiplexer selects the inputs.

The below figure shows the block diagram of an 8-to-1 multiplexer with enable input that can enable or disable the multiplexer. Since the number data bits given to the MUX are eight, then 3 bits (2 3 = 8) are needed to select one of the eight data bits.

8×1 Multiplexer Calculator

The 8 to 1 multiplexer truth table is given below with eight combinations of inputs so as to generate each output corresponds to input.

For example, if S2= 0, S1=1 and S0=0 then the data output Y is equal to D2. Similarly the data outputs D0 to D7 will be selected through the combinations of S2, S1 and S0 as shown in below figure.

From the above 8:1 multiplexer truth table, the Boolean equation for the output is given as:

From the above Boolean equation, the logic circuit diagram of an 8-to-1 multiplexer can be implemented by using 8 AND gates, 1 OR gate and 7 NOT gates as shown in below figure. In the circuit, when enable pin is set to one, the multiplexer will be disabled and if it is zero, then select lines will select the corresponding data input to pass through the output.

IC 74151 is a popular 8-to-1 multiplexer IC with eight inputs and two outputs. The two outputs are active low and active high outputs. It has three select lines A, B and C and one active low enable input. The pinout of this IC is given below.

8 to 1 Mux Using 4 to 1 Mux And 2 to 1 Mux

If you observe the Boolean Expression of 8-to-1 Multiplexer shown above, we can re-write it as follows:

The expression in the first bracket i.e.,   S1 S2 D0 + S1 S2 D1 + S1 S2 D2 + S1 S2 D3  is similar to the multiplexer Boolean Expression of a 4-to-1 Multiplexer with D0, D1, D2 and D3 as inputs and S1 and S2 as Select Lines. Let this expression be P1.

Similarly, the expression in the second bracket i.e.,   S1 S2 D4 + S1 S2 D5 + S1 S2 D6 + S1 S2 D7  is similar to the multiplexer Boolean Expression of another 4-to-1 Multiplexer with D4, D5, D6 and D7 as inputs and S1 and S2 as Select Lines. Let this expression be P2.

Now, replacing the above expressions with P1 and P2, we get,

This expression is similar to a 2-to-1 Multiplexer with P1 and P2 (where, P1 and P2 are outputs of respective 4-to-1 Multiplexers) as Inputs and S0 as Select Signal. So, finally, we can deduce that an 8-to-1 Multiplexer can be implemented using two 4-to-1 Multiplexers and one 2-to-1 Multiplexer. The block diagram of the same is shown below:

16 to 1 Multiplexer

All the higher order Multiplexers like 8-to-1, 16-to-1, etc. can be implemented using lower order multiplexers. But none the less, let us take a quick look at 16-to-1 Multiplexer. IC 74150 is a popular 16-to-1 Multiplexer IC. The inputs to a 16:1 MUX are D0, D1, D2 and so on up tp D15. Since it has 16 input lines, there will be 4 select lines namely S0, S1, S2 and S3.

The following image shows the block diagram of a typical 16 to 1 Multiplexer.

Simplified truth table for 16×1 Multiplexer is shown in the following table.

The Boolean Expression of a 16-to-1 Multiplexer is as follows:

The following image shows the logical circuit of a 16-to-1 Multiplexer.

Similar to an 8-to-1 Multiplexer, we can implement 16-to-1 Multiplexer using lower order multiplexers like 8-to-1, 4-to-1 and 2-to-1. The following image shows the block diagram of a 16-to-1 Multiplexer implemented using two 8-to-1 Multiplexers and one 2-to-1 Multiplexer.

Further, we can implement the individual 8-to-1 Multiplexers in the above image using two 4-to-1 Multiplexers and one 2-to-1 Multiplexer.

Application of Multiplexer

In all types of digital system applications, multiplexers find its immense usage. Since these allows multiple inputs to be connected independently to a single output, multiplexers are found in variety of applications including data routing, logic function generators, control sequencers, parallel-to-serial converters, etc.

Multiplexers are used in telecommunications for data routing, in computer memory to select data lines, in broadcasting to combine multiple audio or video signals, and in various electronic devices for signal processing.

Data Routing

Multiplexers are extensively used in data routing applications to route the data to a one particular destination from one of several sources. One of the applications includes the displaying of two multidigit BCD counters, one at a time. In such application, 74157 multiplexer ICs are used to select and display the content of either of two BCD counters using a set of decoder and LED displays.

Logic Function Generator

In place of logic gates, a logical expression can be generated by using a multiplexer. It is possible to connect the multiplexer such that it duplicates the logic of any truth table. In such cases it can generate the Boolean algebraic function of a set of input variables.

This abruptly reduces the number of logic gates or integrated circuits to perform the logic function since the multiplexer is a single integrated circuit. In this kind of applications, multiplexers are viewed as logic function generators.

For example consider the below logic diagram to implement the ex-OR function of three inputs. A 74151A 8-to-1 multiplexer is used in this logic generator. This multiplexer works exactly similar to the set of logic gates implementing the same function.

The output F is 1 for data inputs D1, D2, D5 and D6 which are selected by making selection lines to 001, 010, 100 and 111 respectively.

Parallel to Serial Conversion

A multiplexer circuit can be used to convert the parallel data to serial data in order to reduce the number of parallel buses by converting them to serial signals. This type of conversion is needed in telecommunication, test and measurement, military/aerospace, data communications applications.

Mostly in digital systems, data is processed in parallel for achieving higher speeds. But for transmission of the data signals over long distances, we need more number of lines. In such cases, parallel data is converted into serial form using multiplexers.

The figure below shows the parallel to serial data conversion using an 8 input multiplexer. Parallel data from the data in or some other register is applied to the 8 input lines of the multiplexer.

The selection codes for the multiplexer are generated by a 3-bit counter. With the application of each clock pulse to the counter the data is serially out from the multiplexer.

Other applications of multiplexers include control sequencers, pulse train generators, encoders, register to register data transfer, waveform generators, etc.

Complete tutorial on Multiplexer (MUX) and Multiplexing. You learned the basics of Multiplexing, multiplexer, different types of commonly used multiplexers like 2:1 MUX, 4:1 MUX, 8:1 MUX and 16:1 MUX, their multiplexer Boolean Expressions, logic circuits and also couple of important applications of Multiplexers.

FAQs: Multiplexers And Multiplexing

How does a multiplexer differ from a demultiplexer?

A multiplexer (MUX) combines multiple input signals into one output signal, while a demultiplexer (DEMUX) takes a single input signal and routes it to one of several outputs.

What are the key factors to consider when selecting a multiplexer for a project?

Key factors include the number of input channels, signal type (analog or digital), speed requirements, power consumption, and compatibility with the rest of the system.

How does a multiplexer improve the efficiency of data transmission?

A multiplexer allows multiple signals to be transmitted over a single channel, reducing the need for multiple communication lines and improving bandwidth efficiency.

How do multiplexers affect signal integrity?

Multiplexers can introduce signal degradation due to factors like crosstalk, noise, and propagation delay. Proper design and shielding can mitigate these effects.

Are there software-based multiplexers?

Yes, software-based multiplexers exist and are used in applications like operating systems and networking software to manage multiple data streams and virtual channels.

Related Posts:

• Multiplexer And Demultiplexer: Types and Differences
• Introduction to Combinational Logic Circuits
• Audio Equalizer Circuit
• What Is A Demultiplexer (Demux)?
• Wireless Communication: Introduction, Types and Applications
• Modulation and Different Types of Modulation

17 Responses

can u explain 16 to 1 multiplexer

Yes. 16 to 1 multiplexer is a 16 to 1 multiplexer.

The content is good

Thanks for giving us such kind of imp. Information

It’s helpful

how to implement mux into full adder / full subtractor and half adder/ half subtractor.

Can u explain 6-1 multiplexer

Can you please explain 3×4 multiplexer

can u plzz explain 16:1 multiplexer

Can u add 10×1 plizz

thanx for this information..very helpful content and easy to understand

thank you for this info.and very helpful content easy to understand

very helpful content easy to understand

Great explanation! Finally i understand this logic gate in depth.

it is simple and understandable easily. it’s giving more information. thank you

Excellent article.

Caught a little error. The logical circuit of a 4-to-1 MUX represents the S1 line as S0.

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Get our Latest Newletters

Get great content that you love. No ads or spams, we promise.

How To Guides

Android Apple Windows Email YouTube Instagram SnapChat Gaming Discord Cloud Storage Google Sheets

Product Reviews

Home & Security Camera Motherboard PC & PC Accessories Laptops Speakers Car Accessories Air Conditioner Lawn & Garden Software Modem & Router

For Students

Electronics Projects Arduino Projects Embedded Free Circuits Mini Projects Robotics Sensor Cables & Wires RV Systems Solar

Interesting

Insights Tutorials Upcoming Sales Usernames Symbols Calculators Courses Deals Our Story

• Affiliate Disclosure
• Terms and Conditions
• Privacy Policy

Copyright © 2024 Electronicshub.org

• Engineering Mathematics
• Discrete Mathematics
• Operating System
• Computer Networks
• Digital Logic and Design
• C Programming
• Data Structures
• Theory of Computation
• Compiler Design
• Computer Org and Architecture

Multiplexers in Digital Logic

In this article we will go through the multiplexer, we will first define what is a multiplexer then we will go through its types which are 2×1 and 4×1, then we will go through the Implementation of the 2×1 mux and higher mux with lower order mux, At last we will conclude our article with some applications, advantages and some FAQs.

Table of Content

What Are Multiplexers?

Types of mux, 2×1 multiplexer, 4×1 multiplexer, implementation of different gates with 2:1 mux.

• Implementation of Higher Order MUX using Lower Order MUX 

Advantages and Disadvantages of MUX

A multiplexer is a combinational circuit that has many data inputs and a single output, depending on control or select inputs. For N input lines, log2(N) selection lines are required, or equivalently, for [Tex]2^n[/Tex] input lines, n selection lines are needed. Multiplexers are also known as “N-to-1 selectors,” parallel-to-serial converters, many-to-one circuits, and universal logic circuits. They are mainly used to increase the amount of data that can be sent over a network within a certain amount of time and bandwidth .

Multiplexer

The Mux can be of different types based on input but in this article we will go through two major types of mux which are

• 2×1 Mux
• 4×1 Mux

The 2×1 is a fundamental circuit which is also known 2-to-1 multiplexer that are used to choose one signal from two inputs and transmits it to the output. The 2×1 mux has two input lines, one output line, and a single selection line. It has various applications in digital systems such as in microprocessor it is used to select between two different data sources or between two different instructions.

Block Diagram of 2:1 Multiplexer with Truth Table

Given Below is the Block Diagram and Truth Table of 2:1 Mux. In this Block Diagram where I0 and I1 are the input lines ,Y is the output line and S0 is a single select line.

The output of the 2×1 Mux will depend on the selection line S0,

• When S is 0(low), the I0 is selected
• when S0 is 1(High), I1 is selected

Logical Expression of 2×1 Mux

Using the Truth Table ,the Logical Expression for Mux can be determined as

[Tex]Y=\overline{S_0}.I_0+S_0.I_1[/Tex]

Circuit Diagram of 2×1 Multiplexers

Using truth table the circuit diagram can be given as

Circuit Diagram of 2×1 Mux

The 4×1 Multiplexer which is also known as the 4-to-1 multiplexer. It is a multiplexer that has 4 inputs and a single output. The Output is selected as one of the 4 inputs which is based on the selection inputs. The number of the Selection lines will depend on the number of the input which is determined by the equation [Tex]log_2n[/Tex] ,In 4×1 Mux the selection lines can be determined as [Tex]log_4=2[/Tex] ,slo two selections are needed.

Block Diagram of 4×1 Multiplexer

In the Given Block Diagram I0, I1, I2, and I3 are the 4 inputs and Y is the Single output which is based on Select lines S0 and S1.

The output of the multiplexer is determined by the binary value of the selection lines

• When S1S0=00, the input I0 is selected.
• When S1S0=01, the input I1 is selected.
• When S1S0=10, the input I2 is selected.
• When S1S0=11, the input I3 is selected.

Truth Table of 4×1 Multiplexer

Given Below is the Truth Table of 4×1 Multiplexer

Circuit Diagram of 4×1 Multiplexers

Using truth table the circuit diagram can be given as  

Multiplexer can act as universal combinational circuit. All the standard logic gates can be implemented with multiplexers. 

Given below are the Implementation of Different gate using 2:1 Mux

Implementation of NOT gate using 2 : 1 Mux

The Not gate from 2:1 Mux can be obtained by

• Connect the input signal to one of the data input lines(I0).
• Then connect a line (0 or 1) to the other data input line(I1)
• Connect the same input line Select line S0 which is connected to D0.

Given Below is the Diagram for the Logical Representation of NOT gate using 2 : 1 Mux

Implementation of AND gate using 2 : 1 Mux

The And gate from 2:1 Mux can be obtained by

• Connect the input Y to I1.
• Connect the input X to the selection line S0.
• Connect a line(0) to I0.

Given Below is the Diagram for the Logical Representation of AND gate using 2 : 1 Mux  

For further more on the Implementation of AND gate using 2 : 1 Mux  

Implementation of OR gate using 2 : 1 Mux

The OR gate from 2:1 Mux can be obtained by  

• Connect input X to the selection line S0.
• Connect input Y to I1.
• Connect Line(1) to I1.

Given Below is the Diagram for the Logical Representation of OR gate using 2 : 1 Mux

Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux. First multiplexer will act as NOT gate which will provide complemented input to the second multiplexer.   

Implementation of NAND gate using 2 : 1 Mux

The NAND gate from 2:1 Mux can be obtained by  

• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I1.
• line(1) is given to the I0.
• x is given as selection line for the second Mux.

Given Below is the Diagram for the Logical Representation of NAND gate using 2 : 1 Mux  

For further more on the Implementation of NAND gate using 2 : 1 Mux  

Implementation of NOR gate using 2 : 1 Mux

The Nor gate from 2:1 Mux can be obtained by  

• In Second MUX the Output from mux is connected to I0.
• line(0) is given to the I1.

Given Below is the Diagram for the Logical Representation of NOR gate using 2 : 1 Mux  

For further more on the Implementation of NOR gate using 2 : 1 Mux

Implementation of EX-OR gate using 2 : 1 Mux

• y is given to the I0.

Given Below is the Diagram for the Logical Representation of EX-OR gate using 2 : 1 Mux  

Implementation of EX-NOR gate using 2 : 1 Mux

Given Below is the Diagram for the Logical Representation of EX-OR gate using 2 : 1 Mux

• y is given to the I1.

Implementation of Higher Order MUX using Lower Order MUX  

Given Below are the Implementation of Higher Order MUX Using Lower Order MUX

4 : 1 MUX using 2 : 1 MUX

Three 2: 1 MUX are required to implement 4 : 1 MUX.   

Similarly,  While an 8:1 MUX requires seven (7) 2:1 MUXes, a 16:1 MUX requires fifteen (15) 2:1 MUXes, and a 64:1 MUX requires sixty-three (63) 2:1 MUXes. Hence, we can draw the conclusion that an [Tex]2^n:1[/Tex] MUX requires [Tex](2^n-1) 2:1 MUXes[/Tex] .  

16 : 1 MUX using 4 : 1 MUX  

Given Below is the logical Diagram of 16:1 Mux Using 4:1 Mux

In general, to implement B : 1 MUX using A : 1 MUX , one formula is used to implement the same.  B / A = K1,  K1/ A = K2,  K2/ A = K3  K N-1 / A = K N = 1 (till we obtain 1 count of MUX).  And then add all the numbers of MUXes = K1 + K2 + K3 + …. + K N .  To implement 64 : 1 MUX using 4 : 1 MUX  Using the above formula, we can obtain the same.  64 / 4 = 16  16 / 4 = 4  4 / 4 = 1 (till we obtain 1 count of MUX)  Hence, total number of 4 : 1 MUX are required to implement 64 : 1 MUX = 16 + 4 + 1 = 21.  f ( A, B, C) = [Tex]\sum[/Tex] ( 1, 2, 3, 5, 6 ) with don’t care (7)

using A and B as the select lines for 4 : 1 MUX,

AB as select: Expanding the minterms to its boolean form and will see its 0 or 1 value in Cth place so that they can be placed in that manner.  

AC as select : Expanding the minterms to its boolean form and will see its 0 or 1 value in Bth place so that they can be place in that manner.   

BC as select : Expanding the minterms to its boolean form and will see its 0 or 1 value in A th place so that they can be place in that manner.   

Given below are the Advantages and Disadvantages of MUX

Advantages of MUX

Given below are the Advantages of MUX

• Efficiency : The Mux has good efficiency in routing multiple input signals to a single out signal based on control signals.
• Optimization : The Mux helps to conserve resources such as wires, pins and integrated circuit (IC).
• Different Implementation: The Mux can be used to implement different digital logic functions such AND,OR etc.
• Flexibility: Mux can be easily configure according to the requirements and accommodate different data sources, enhancing system versatility.

Disadvantages of MUX

Given Below are the Disadvantages of MUX

• Limited number of data sources:  The number of input that can be taken by a multiplexer is restricted by the number of control lines, which can cause limitations in certain applications.
• Delay:  Multiplexers can have some delay in the signal path, which can have impact on the performance of the circuit.
• Complex control rationale:  The control logic for multiplexers can be complex, particularly for bigger multiplexers with an large number of inputs.
• Power utilization:  Multiplexers can consume more power compared with other simple l ogic gate , particularly when they have a large number of inputs.

Applications of MUX

Given Below are the Applications of MUX

• Data Routing : The Mux is used for data routing in the digital system where they select one of the several data lines and re-route it the output.
• Data Selection : The Mux is used for data selection where they select data source according to the select lines.
• Analog-to-Digital Conversion : The Mux are used in ADC to select different analog input channels.
• Address Decoding : The Mux are used in Microprocessors or memory for address decoding.
• Logic Function Implementation : Muxes can be used to implement various logic functions.

In this Article we have gone through the MUX, we have seen Different Types of Mux which are 2×1 and 4×1 Mux, we have gone through the implementation of the 2×1 mux and higher mux with lower order mux. Also we have gone through its Advantages, Disadvantages and Applications in brief.

Multiplexers in Digital Logic – FAQs

Why is the control logic for multiplexers is considered complex.

The Mux can be complex especially for larger multiplexers because of the control signals which select inputs based on the application requirements.

What are the different types of multiplexer architectures?

Mux architectures are changed on factors such as the total number of inputs, the number of select lines and the logic used for input selection.

How do multiplexers are used digital signal processing (DSP) applications?

In DSP applications, multiplexers are used for signal routing, selection, and processing.

Please Login to comment...

Similar reads.

• Digital Logic
• How to Get a Free SSL Certificate
• Best SSL Certificates Provider in India
• Elon Musk's xAI releases Grok-2 AI assistant
• What is OpenAI SearchGPT? How it works and How to Get it?
• Content Improvement League 2024: From Good To A Great Article

Improve your Coding Skills with Practice

What kind of Experience do you want to share?