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VLSI research papers IEEE PAPER

Vlsi projects, vlsi research papers 2018, vlsi-research papers 2016, vlsi-research papers 2015, vhdl research papers.

• VHDL approach to performance analysis of fuzzy logic controllers
• VHDL design and simulation of a fast beam loss interlock for TTF2
• Supporting VHDL Design for Air-Conditioning Controller Using Evolutionary Computation
• Array OL Descriptions of Repetitive Structures in VHDL
• Constrained Random Verification with VHDL
• Fundamentals of DIGITAL LOGIC with VHDL design
• Electromechanical modeling beyond VHDL
• Partitioning for multicomponent synthesis from VHDL specifications
• VHDL-AMS for mixed technology and mixed signal, an overview
• Assisting network intrusion detection with reconfigurable hardware
• VHDL-AMS in MEMS design flow
• OO-VHDL An Object Oriented VHDL
• Verification of COMBO6 VHDL Design
• VHDL modelling of a fuzzy co-processor architecture
• FPGAs Implementation of a digital IQ demodulator using VHDL
• Assessing the potential of multi-threaded VHDL simulation
• Proof theory and a validation condition generator for VHDL
• Objective VHDL-tools and applications
• Using a vhdl testbench for transistor-level simulation and energy calculation
• bject-Oriented Extensions to VHDL
• Energy-based characterization of microelectromechanical systems
• Experiences with VHDL Models of COTS RISC Processors in Virtual Prototyping for Complex System Synthesis
• Information flow analysis for VHDL
• A structured VHDL design method
• A Formalization of a Subset of VHDL in the Boyer-Moore Logic
• Implementing a petri net specification in a fpga using vhdl
• IAV- A VHDL methodology for FPGA implementation
• Static Analysis of VHDL Model Evaluation
• A model driven engineering design flow to generate VHDL
• A VHDL implementation of an on-board ACF application targeting FPGAs
• On the reuse of VHDL modules into systemC designs
• VHDL-based performance modeling and virtual prototyping
• An evolutionary approach to automatic generation of VHDL code for low-power digital filters
• Fault modeling and simulation using VHDL-AMS
• An object-oriented view of structural VHDL description
• Multi-level fault injections in VHDL descriptions: alternative approaches and experiments
• State machine design techniques for Verilog and VHDL

FPGA RESEARCH PAPERS FREE

• free research papers and research projects on FPGA
• A case study in hardware Trojan design and implementation
• Design and Implementation of Vision-Based Fuzzy Obstacle Avoidance Method on Humanoid Robot
• FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques
• FPGA based UWB MISO time-reversal system design and implementation
• Design a simple calculator using fpga
• FPGA-based spectral envelope preprocessor for power monitoring and control
• FPGA acceleration for the frequent item problem
• Technology mapping and clustering for FPGA architectures with dual supply voltages
• FPGA-based set-up for RF power amplifier dynamic Supply with real-time digital adaptive pre distortion
• An interface methodology for retargettable fpga peripherals
• Using Hard Macros to Reduce FPGA Compilation Time
• RAMP Gold: An FPGA-based architecture simulator for multiprocessors
• FPGA design and implementation of a real-time stereo vision system
• Secure extension of FPGA soft core processors for symmetric key cryptography
• FPGA Based Control of a Self Starting CSI Fed 2kW, 9.8 kHz Induction Heating Unit
• Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
• FPGA Design and Implementation of Dense Matrix-Vector Multiplication for Image Processing Application
• Design of a Real Time FPGA-based Three Dimensional Positioning Algorithm

ASIC- APPLICATION SPECIFIC INTEGRATED CIRCUIT

• ASIC and FPGA implementations of H. 264 DCT and quantization blocks
• Impact of interconnect pattern density information on a 90nm technology ASIC design flow
• The coincidence matrix ASIC of the level-1 muon barrel trigger of the ATLAS experiment
• A flexible multi-channel high-resolution time-to-digital converter ASIC
• Leakage power estimation for deep submicron circuits in an ASIC design environment
• Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders
• ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs
• Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements
• Receiver ASIC for timing, trigger and control distribution in LHC experiments
• Performance of a low noise front-end ASIC for Si/CdTe detectors in Compton gamma-ray telescope
• Secure contactless smartcard ASIC with DPA protection
• Selectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance
• AN ASIC IMPLEMENTATION OF THE TWO-DIMENSIONAL DISCRETE COSINE TRANSFORM
• Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE
• Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

VLSI simulation projects

• Power estimation in VLSI circuits
• Parallel logic simulation of VLSI systems
• simulation of VLSI networks
• Crosstalk Delay Faults in vlsi
• power distribution network in VLSI circuits
• VLSI interconnect lines
• stochastic neurons in VLSI

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Computer Science > Artificial Intelligence

Title: automated design of agentic systems.

Abstract: Researchers are investing substantial effort in developing powerful general-purpose agents, wherein Foundation Models are used as modules within agentic systems (e.g. Chain-of-Thought, Self-Reflection, Toolformer). However, the history of machine learning teaches us that hand-designed solutions are eventually replaced by learned solutions. We formulate a new research area, Automated Design of Agentic Systems (ADAS), which aims to automatically create powerful agentic system designs, including inventing novel building blocks and/or combining them in new ways. We further demonstrate that there is an unexplored yet promising approach within ADAS where agents can be defined in code and new agents can be automatically discovered by a meta agent programming ever better ones in code. Given that programming languages are Turing Complete, this approach theoretically enables the learning of any possible agentic system: including novel prompts, tool use, control flows, and combinations thereof. We present a simple yet effective algorithm named Meta Agent Search to demonstrate this idea, where a meta agent iteratively programs interesting new agents based on an ever-growing archive of previous discoveries. Through extensive experiments across multiple domains including coding, science, and math, we show that our algorithm can progressively invent agents with novel designs that greatly outperform state-of-the-art hand-designed agents. Importantly, we consistently observe the surprising result that agents invented by Meta Agent Search maintain superior performance even when transferred across domains and models, demonstrating their robustness and generality. Provided we develop it safely, our work illustrates the potential of an exciting new research direction toward automatically designing ever-more powerful agentic systems to benefit humanity.

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Software Engineering Institute

Sei digital library, latest publications, embracing ai: unlocking scalability and transformation through generative text, imagery, and synthetic audio, august 28, 2024 • webcast, by tyler brooks , shannon gallagher , dominic a. ross.

In this webcast, Tyler Brooks, Shannon Gallagher, and Dominic Ross aim to demystify AI and illustrate its transformative power in achieving scalability, adapting to changing landscapes, and driving digital innovation.

Counter AI: What Is It and What Can You Do About It?

August 27, 2024 • white paper, by nathan m. vanhoudnos , carol j. smith , matt churilla , shing-hon lau , lauren mcilvenny , greg touhill.

This paper describes counter artificial intelligence (AI) and provides recommendations on what can be done about it.

Using Quality Attribute Scenarios for ML Model Test Case Generation

August 27, 2024 • conference paper, by rachel brower-sinning , grace lewis , sebastián echeverría , ipek ozkaya.

This paper presents an approach based on quality attribute (QA) scenarios to elicit and define system- and model-relevant test cases for ML models.

3 API Security Risks (and How to Protect Against Them)

August 27, 2024 • podcast, by mckinley sconiers-hasan.

McKinley Sconiers-Hasan discusses three API risks and how to address them through the lens of zero trust.

Lessons Learned in Coordinated Disclosure for Artificial Intelligence and Machine Learning Systems

August 20, 2024 • white paper, by allen d. householder , vijay s. sarvepalli , jeff havrilla , matt churilla , lena pons , shing-hon lau , nathan m. vanhoudnos , andrew kompanek , lauren mcilvenny.

In this paper, the authors describe lessons learned from coordinating AI and ML vulnerabilities at the SEI's CERT/CC.

On the Design, Development, and Testing of Modern APIs

July 30, 2024 • white paper, by alejandro gomez , alex vesey.

This white paper discusses the design, desired qualities, development, testing, support, and security of modern application programming interfaces (APIs).

Evaluating Large Language Models for Cybersecurity Tasks: Challenges and Best Practices

July 26, 2024 • podcast, by jeff gennari , samuel j. perl.

Jeff Gennari and Sam Perl discuss applications for LLMs in cybersecurity, potential challenges, and recommendations for evaluating LLMs.

Capability-based Planning for Early-Stage Software Development

July 24, 2024 • podcast, by anandi hira , bill nichols.

This SEI podcast introduces capability-based planning (CBP) and its use and application in software acquisition.

A Model Problem for Assurance Research: An Autonomous Humanitarian Mission Scenario

July 23, 2024 • technical note, by gabriel moreno , anton hristozov , john e. robert , mark h. klein.

This report describes a model problem to support research in large-scale assurance.

Safeguarding Against Recent Vulnerabilities Related to Rust

June 28, 2024 • podcast, by david svoboda.

David Svoboda discusses two vulnerabilities related to Rust, their sources, and how to mitigate them.

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NVIDIA to Present Innovations at Hot Chips That Boost Data Center Performance and Energy Efficiency

A deep technology conference for processor and system architects from industry and academia has become a key forum for the trillion-dollar data center computing market.

At Hot Chips 2024 next week, senior NVIDIA engineers will present the latest advancements powering the NVIDIA Blackwell platform, plus research on liquid cooling for data centers and AI agents for chip design.

They’ll share how:

• NVIDIA Blackwell brings together multiple chips, systems and NVIDIA CUDA software to power the next generation of AI across use cases, industries and countries.
• NVIDIA GB200 NVL72 — a multi-node, liquid-cooled, rack-scale solution that connects 72 Blackwell GPUs and 36 Grace CPUs — raises the bar for AI system design.
• NVLink interconnect technology provides all-to-all GPU communication, enabling record high throughput and low-latency inference for generative AI.
• The NVIDIA Quasar Quantization System pushes the limits of physics to accelerate AI computing.
• NVIDIA researchers are building AI models that help build processors for AI.

An NVIDIA Blackwell talk, taking place Monday, Aug. 26, will also spotlight new architectural details and examples of generative AI models running on Blackwell silicon.

It’s preceded by three tutorials on Sunday, Aug. 25, that will cover how hybrid liquid-cooling solutions can help data centers transition to more energy-efficient infrastructure and how AI models, including large language model (LLM)-powered agents, can help engineers design the next generation of processors.

Together, these presentations showcase the ways NVIDIA engineers are innovating across every area of data center computing and design to deliver unprecedented performance, efficiency and optimization.

Be Ready for Blackwell

NVIDIA Blackwell is the ultimate full-stack computing challenge. It comprises multiple NVIDIA chips, including the Blackwell GPU, Grace CPU, BlueField data processing unit, ConnectX network interface card, NVLink Switch , Spectrum Ethernet switch and Quantum InfiniBand switch.

Ajay Tirumala and Raymond Wong, directors of architecture at NVIDIA, will provide a first look at the platform and explain how these technologies work together to deliver a new standard for AI and accelerated computing performance while advancing energy efficiency.

The multi-node NVIDIA GB200 NVL72 solution is a perfect example. LLM inference requires low-latency, high-throughput token generation. GB200 NVL72 acts as a unified system to deliver up to 30x faster inference for LLM workloads, unlocking the ability to run trillion-parameter models in real time.

Tirumala and Wong will also discuss how the NVIDIA Quasar Quantization System — which brings together algorithmic innovations, NVIDIA software libraries and tools, and Blackwell’s second-generation Transformer Engine — supports high accuracy on low-precision models, highlighting examples using LLMs and visual generative AI.

Keeping Data Centers Cool

The traditional hum of air-cooled data centers may become a relic of the past as researchers develop more efficient and sustainable solutions that use hybrid cooling, a combination of air and liquid cooling.

Liquid-cooling techniques move heat away from systems more efficiently than air, making it easier for computing systems to stay cool even while processing large workloads. The equipment for liquid cooling also takes up less space and consumes less power than air-cooling systems, allowing data centers to add more server racks — and therefore more compute power — in their facilities.

Ali Heydari, director of data center cooling and infrastructure at NVIDIA, will present several designs for hybrid-cooled data centers.

Some designs retrofit existing air-cooled data centers with liquid-cooling units, offering a quick and easy solution to add liquid-cooling capabilities to existing racks. Other designs require the installation of piping for direct-to-chip liquid cooling using cooling distribution units or by entirely submerging servers in immersion cooling tanks. Although these options demand a larger upfront investment, they lead to substantial savings in both energy consumption and operational costs.

Heydari will also share his team’s work as part of COOLERCHIPS , a U.S. Department of Energy program to develop advanced data center cooling technologies. As part of the project, the team is using the NVIDIA Omniverse platform to create physics-informed digital twins that will help them model energy consumption and cooling efficiency to optimize their data center designs.

AI Agents Chip In for Processor Design

Semiconductor design is a mammoth challenge at microscopic scale. Engineers developing cutting-edge processors work to fit as much computing power as they can onto a piece of silicon a few inches across, testing the limits of what’s physically possible.

AI models are supporting their work by improving design quality and productivity, boosting the efficiency of manual processes and automating some time-consuming tasks. The models include prediction and optimization tools to help engineers rapidly analyze and improve designs, as well as LLMs that can assist engineers with answering questions, generating code, debugging design problems and more.

Mark Ren, director of design automation research at NVIDIA, will provide an overview of these models and their uses in a tutorial. In a second session, he’ll focus on agent-based AI systems for chip design.

AI agents powered by LLMs can be directed to complete tasks autonomously, unlocking broad applications across industries. In microprocessor design, NVIDIA researchers are developing agent-based systems that can reason and take action using customized circuit design tools, interact with experienced designers, and learn from a database of human and agent experiences.

NVIDIA experts aren’t just building this technology — they’re using it . Ren will share examples of how engineers can use AI agents for timing report analysis, cell cluster optimization processes and code generation . The cell cluster optimization work recently won best paper at the first IEEE International Workshop on LLM-Aided Design .

Register for Hot Chips , taking place Aug. 25-27, at Stanford University and online.

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iii Time-Saver Standards for Architectural Design Data Time-Saver Standards for Architectural Design Data seventh edition The Reference of Architectural Fundamentals

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